Re: [vhdl-200x] Please Review Matrix Math Package

On 06/23/2014 02:43 AM, Scott Hoy wrote:
> Is there any thoughts to add a ".*" or "./" operators to VHDL that mirrors
> the behavior of a well known algorithm development tool?
We had a discussion about this in the telecon today.   Yes these are 
useful operations.   The problem is that creating new operators in VHDL 
is hard to do.
In Matlab:
.* = times
./ = rdivide
So I used those names for these functions.

> One other question,
> are there any plans to add the remaining rounding modes to the fixed-point
> data types that is supported in SystemC and the well known algorithm
> development tool? To my knowledge the only fixed point rounding modes
> supported in VHDL are truncate and rounding which from a hardware standpoint
> are the two that require the least amount of logic.  This would make
> cosimulating fixed-point models in VHDL and SystemC to maintain bit accuracy
> since they have access to the same fixed point rounding modes.  Does anyone
> know if the Verilog/System Verilog ever plan to support a native fixed-point
> or floating point data type?  From my own investigation into this, I
> currently see no plan.
>
In the fixed point packages the only rounding modes available are 
"truncate" (IEEE Round 0) and "round" (actually the IEEE round nearest 
algorithm is used).
In the floating point packages you have 4, round_nearest, round_zero, 
round_positive, and round_negative.   These are from IEEE 854.
Unknown to us, as we were updating IEEE-1076-2008 there was also an 
IEEE-854-2008.  This one described two more rounding modes, as well as 
decimal floating point.

The Verilog and SV people have already approached me to write these 
packages for them.   Right now there are major language barriers as to 
why this can't be done.


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