RE: [vhdl-200x] Please Review Matrix Math Package

From: Scott Hoy <sdhoy@verizon.net>
Date: Sun Jun 22 2014 - 23:43:56 PDT
Is there any thoughts to add a ".*" or "./" operators to VHDL that mirrors
the behavior of a well known algorithm development tool? One other question,
are there any plans to add the remaining rounding modes to the fixed-point
data types that is supported in SystemC and the well known algorithm
development tool? To my knowledge the only fixed point rounding modes
supported in VHDL are truncate and rounding which from a hardware standpoint
are the two that require the least amount of logic.  This would make
cosimulating fixed-point models in VHDL and SystemC to maintain bit accuracy
since they have access to the same fixed point rounding modes.  Does anyone
know if the Verilog/System Verilog ever plan to support a native fixed-point
or floating point data type?  From my own investigation into this, I
currently see no plan.

Regards,

Scott D. Hoy
E-mail: sdhoy@verizon.net 

-----Original Message-----
From: owner-vhdl-200x@eda.org [mailto:owner-vhdl-200x@eda.org] On Behalf Of
Jim Lewis
Sent: Sunday, June 22, 2014 2:31 PM
To: vhdl-200x@eda.org
Subject: [vhdl-200x] Please Review Matrix Math Package

Hi,
Please review the proposed matrix math package.  It is proposed to become
part of IEEE 1076 and is a necessary part for the 1076.1 VHDL-AMS standard.

You can find the user guide here:
http://www.vhdl.org/fphdl/real_matrix_ug.pdf

You can find the packages here:
http://www.vhdl.org/fphdl/real_matrix_pkg.zip

Speak now and be heard - otherwise don't complain later.

Best Regards,
Jim
-- 
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Jim Lewis                                  Jim@SynthWorks.com
VHDL Training Expert                       http://www.SynthWorks.com
IEEE VHDL Working Group Chair
OSVVM, Chief Architect and Cofounder
1-503-320-0782
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

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Received on Sun Jun 22 23:44:45 2014

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