Greetings all, I have a couple of comments about the package... Firstly, (having spent too many hours swapping between Matlab, C, and VHDL), I would prefer this function and others like it to have their arguments named differently: Result := submatrix (arg, x, y, rows, columns) "X" and "y" should be called "row" and "column" (or even "start_row" and "start_column"). Any time x and y are used, there's likely to be confusion (esp. if the matrix represents image data :) I feel strongly that "x" and "y" should not be used at all in the library or documentation. Rows and columns are very definitely matrix-related language and should be used throughout. Secondly, the "initialising" functions like "zeros()" currently take in two dimensions. I would think it would be useful if they could also take in an existing matrix to copy the dimensions from - or at least the 'length array of an existing matrix, rather than passing both A'length(1) and A'length(2). Cheers, Martin From: owner-vhdl-200x@eda.org [mailto:owner-vhdl-200x@eda.org] On Behalf Of Jim Lewis Sent: 29 May 2014 19:43 To: vhdl-200x@eda.org Cc: ZHICHAO DENG; Ernst Christen; David Bishop Subject: [vhdl-200x] FWD: About the vector matrix package support for VHDL-AMS and VHDL Hi All, To support 1076.1 effort, David Bishop has generated a vector/matrix package. It is available at: http://www.vhdl.org/fphdl 1076.1 group will be going to standardization some time later this year. The 1076.1 group is offering us the opportunity to review and approve the package before it comes part of 1076.1 - with the intention that it also become part of the 1076. Given the 1076.1 time frame, I suggest that we start reviewing the package now. If you are interested in participating, it would be best to review the package on your own ASAP and then we will review it in the meeting to collect issues and concerns. If you are interested in participating in the review of this and cannot make the regularly scheduled 1076 meetings, please let me know a time frame that would work. Best Regards, Jim Hi Jim, David and Ernst, I am now planning to have some discussion with you two to set up a time table, which is acceptable to both VHDL and VHDL-AMS group. The remaining work for vector/matrix package is mostly about finalizing the functions needed for both group and some naming conventions. Do you think that sometime next week will be a good time? Or you prefer exchanging the ideas through emails first. Regards, Zhichao On Wed, May 14, 2014 at 8:57 AM, Jim Lewis <Jim@synthworks.com<mailto:Jim@synthworks.com>> wrote: Hi Zhicago, Yes. My meeting time is problematic though. I mainly have later in the day, after 3 pm Pacific this week. Next week I will be at a conference Monday through Thursday. Jim P.S. I just added you to the group list. As a result, when you login to twiki, you should be able to add yourself to the group roster. Hi Jim Lewis, I wonder whether we could talk sometime about the vector matrix package. Thanks, Zhicago Deng On Apr 18, 2014 12:03 PM, "ZHICHAO DENG" <zhichaodeng@gmail.com<mailto:zhichaodeng@gmail.com>> wrote: Hi Jim and David, I am writing to see what kind of schedule that VHDL has planned for vector-matrix package. VHDL-AMS is planning to incorporate the package if we could finalize it by the end of this year. I would like to get involved in VHDL'a side to help move the project forward. BTW, could you add me to VHDL WG standard's roster? Regards, Zhichao Deng On Thu, Apr 17, 2014 at 7:32 PM, David Bishop <dbishop@vhdl.org<mailto:dbishop@vhdl.org>> wrote: On 4/17/2014 12:22 PM, ZHICHAO DENG wrote: How about calling you around 4:30PM (PST) (7:30PM PST) this evening? Following up on our discussion. The matrix packages are at the bottom of: http://www.vhdl.org/fphdl (Matrix math for type real and integer, these are also packages for complex, complex_polar, ufixed and sfixed) The fixed_alg_pkg and float_alg_pkg convert numbers to real, do the operation, then back to fixed or floating point. There will also be some updates fixed_pkg and float_pkg. -- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Jim Lewis VHDL Training Expert, SynthWorks IEEE 1076 VHDL Working Group Chair Open Source VHDL Verification Methodology (OSVVM), Chief Architect and Co-founder 1-503-320-0782<tel:1-503-320-0782> Jim@SynthWorks.com<mailto:Jim@SynthWorks.com> http://www.SynthWorks.com VHDL Training on leading-edge, best coding practices for hardware design and verification. ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Jim Lewis VHDL Training Expert, SynthWorks IEEE 1076 VHDL Working Group Chair Open Source VHDL Verification Methodology (OSVVM), Chief Architect and Co-founder 1-503-320-0782 Jim@SynthWorks.com<mailto:Jim@SynthWorks.com> http://www.SynthWorks.com VHDL Training on leading-edge, best coding practices for hardware design and verification. ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -- This message has been scanned for viruses and dangerous content by MailScanner<http://www.mailscanner.info/>, and is believed to be clean. -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean.Received on Fri Jun 13 07:03:45 2014
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