Re: [vhdl-200x] Clocked Shorthand Proposal - Need Consensus

Hi Ryan and Jakko,
Thank you for your comments. Personally, I also prefer using 'after' to
introducing another operator. I tend to agree that we should extend
existing syntax in VHDL rather than introducing new ones.

However, I would also like an opinion from the community, hence the reason
for me to bring this up again.

Jakko,
The proposal would mention that if 'after' is used with a time unit, then
it's only for simulation, and no flip-flops will be inferred. Also, if
'after' is used without a time unit, then simulation tools will infer the
amount of time taken in terms of clock cycles, depending on what was set by
the 'clk attribute. In this case, synthesis tools will infer flip flops.

You bring up a good point. We haven't had a discussion on 'mixed' uses such
as
q <= d after 2 after 2 ns;

For this case, I would say synthesis tools would infer 2 flip flops, and
ignore the '2 ns'. For simulation tools, it should infer (2 ns + time taken
by two clock cycles).

Should we require parentheses for scenarios like this?
q <= (d after 2) after 2 ns;

regards, daniel


On 28 March 2014 03:12, <ryan.w.hinton@l-3com.com> wrote:

>  True, there is the possibility of confusion.  There are a few
> differences, though, between the pipelining "after" and the "asynchronous"
> after.  First, the synchronous "after" only works in the new clocked
> process context.  (It would be an interesting exercise to try to generalize
> it -- what should it do in a combinational process or outside a process
> altogether?  I haven't come up with a good answer.)  Also, the "after" used
> in other scenarios always has a time unit.  This one doesn't.  So I don't
> see a potential conflict -- a time when you would want to delay both by a
> number of clocks and a number of nanoseconds.  (What does that even mean?)
>
>
>
> I guess my opinion is that there are plenty of things in VHDL (or any
> language) that can be confusing.  This doesn't seem bad to me.  Again,
> that's my opinion, though.
>
>
>
> - Ryan
>
>
>
> *From:* owner-vhdl-200x@eda.org [mailto:owner-vhdl-200x@eda.org] *On
> Behalf Of *Jakko Verhallen
> *Sent:* Thursday, March 27, 2014 1:01 PM
>
> *To:* vhdl-200x@eda.org
> *Subject:* RE: [vhdl-200x] Clocked Shorthand Proposal - Need Consensus
>
>
>
> Hi Ryan,
>
>
>
> I agree with you, but I have only one remark.
>
> Syntax 1b:
>
> q <= d after 2;
>
> This very much resembles an asynchronous delay like
>
> q <= d after 2 *ns*;
>
>
>
> Although obvious and consistent, this might be confused for an async delay.
>
> Even more, if you want to have 2 cycles delay *and *a async delay, how do
> you model that?
>
> q <= d after 2 after 2 ns?
>
>
>
> I don't like the @ either, so I would rather vote for something like
>
> q <= d *pipe *2 [after 2 ns];
>
>
>
> Jakko
>
>
>
>
>
> *From:* owner-vhdl-200x@eda.org [mailto:owner-vhdl-200x@eda.org] *On
> Behalf Of *ryan.w.hinton@L-3com.com
> *Sent:* Thursday, March 27, 2014 6:54 PM
> *To:* vhdl-200x@eda.org
> *Subject:* RE: [vhdl-200x] Clocked Shorthand Proposal - Need Consensus
>
>
>
> I've been meaning to work on this proposal and add my preferences and
> arguments.  I'll summarize here.
>
>
>
> I *GREATLY* prefer syntax 1b.  What does the @ mean?  Where else is it
> used in VHDL?  Why are we introducing and reserving a new symbol/operator?
> Especially when we already have a reserved keyword "after" whose semantics
> are exactly what we're trying to add (or at least obvious in context).  It
> would be fun to add a new physical constant "cycles" or something.  But I
> assume we won't add that (a) because of English's singular/plural issues,
> e.g. "after 1 cycles", and (b) because I've heard that compilers have fits
> if you try to shadow a physical type.  Someone told me once, "Just try to
> name a signal 'ns' and see what happens!"
>
>
>
> In changing an existing, established, mature language like VHDL, I like to
> make changes as much as possible (1) limited, (2) obvious, and (3)
> consistent.  Perhaps the '@' symbol would make Verilog people happy.  But
> as a VHDL user, I find it neither obvious nor consistent (see my first
> paragraph).  On the other hand, I think 'after' is fairly obvious and
> consistent.  In fact, the consistency helps make it more obvious.
>
>
>
> Now you have my opinion. :-)
>
>
>
> - Ryan
>
>
>
> *From:* owner-vhdl-200x@eda.org [mailto:owner-vhdl-200x@eda.org] *On
> Behalf Of *Daniel Kho
> *Sent:* Thursday, March 27, 2014 11:45 AM
> *To:* vhdl-200x@eda.org
> *Subject:* [vhdl-200x] Clocked Shorthand Proposal - Need Consensus
>
>
>
> Hello,
>
> For the ClockedShorthand<http://www.eda-twiki.org/cgi-bin/view.cgi/P1076/ClockedShorthand>proposal, it seems that Syntax 1 was generally accepted by most people
> during previous discussions.
>
> However, Syntax 1 proposed two different syntaxes which serve the same
> purpose:
>
> Syntax 1a:
>
> q <= d @ 2;
>
> Syntax 1b:
>
> q <= d after 2;
>
> where '2' indicates the number of cycles to delay d before effectively
> driving q.
>
>
>
> I would like to seek your comments on which of the two syntaxes is more
> favourable, and why?
>
> Or does anyone think that both syntaxes should be supported?
>
>
>   regards, daniel
>
>
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