Re: [vhdl-200x] Clocked Shorthand Proposal - Need Consensus

Hi All,
   @ comes from PSL.  Quoting IEEE 1850-2010:

       6.2.1.2 Clocked FL properties
       The FL clock operator operator(@), shown in Syntax 6-18, provides a way to clock an FL Property.
          FL_Property ::= FL_Property @ Clock_Expression

       The first operand is the FL Property to be clocked. The second operand is a Boolean expression with which
       to clock the FL Property.

       The @ operator specifies that the clock expression that is its right operand defines the clock context of its
       left operand.

Hence with '@', we are not introducing a new operator, just recycling the one from PSL.

Personally I prefer expressive code and am not fond of either '@' or "after" since they do not mention Clk.  Who knows though, if the "C/C++" style behavioral synthesis takes hold, maybe we no longer 
need to specify clock in our designs.  Just waiting for someone to do a decent VHDL behavioral synthesis tool.

OTOH, I am not convinced we need any syntax for this.  When you start looking at adding reset, we do not have anything
that is all that much better than:
Q <= D when rising_edge(Clk) ;
   Q <= '0' when not nReset else D when rising_edge(Clk) ;
   Q <= '0' when not nReset and rising_edge(Clk) else D when rising_edge(Clk) ;

Ok, so you loose the pipelining, however, maybe that is what we need the operator for.

If I want more concise, but less expressive code, I can always switch to using a procedure:
   Reg(Clk, D, Q) ;
   RegAr(Clk, not nReset, D, Q) ;
   RegSr(Clk, not nReset, D, Q) ;
   RegR(Clk, not nReset, D, Q) ; -- default reset style choosen by selecting/compiling a particular package body.

   RegPipe(Clk, D, Q, 5) ;

Some of the reset issues would be simplified if synthesis tools provided a mechanism for shifting reset styles.

Jim

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Jim Lewis
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IEEE 1076 VHDL Working Group Chair
Open Source VHDL Verification Methodology (OSVVM), Chief Architect and Co-founder

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