Re: [vhdl-200x] Switch model

Hi Jakko,
That is great.  I understand pass gates.  Not clear what you are doing with the 'Z'.  Is it supposed to be driven onto IN, OUT, or both?  Would it be ok if the drivers simply disconnect and neither A 
nor B contribute anything to the other.  I think this is expressed better by:
A <=> B when S = '1' ;

Also see my reply to Rick.

Thanks,
Jim

> Hi Jim,
>
> Consider a pass gate:
>
> http://upload.wikimedia.org/wikipedia/en/e/e5/CMOS_transmission_gate.PNG
>
> With IN and OUT being unidirectional, this is quite straight forward.
>
> But how do you model this if IN and OUT are bidirectionals (like in real analog design)
>
> (please note that I am not referring to synthesizable code).
>
> The code Brent has sent does solve it, but it will not work if you put 2 in series.
>
> In this picture above, I'd like to be able to use something like
>
> IN <=> OUT when a = '1' else 'Z';
>
> Meaning that IN and OUT are (low-ohmic) connected (indeed not assigned) when the condition is true, meaning that all drivers on IN are also available on OUT.
>
> If the condition is false, IN and OUT are (high-ohmic) disconnected.
>
> Jakko
>
> -----Original Message-----
> From: owner-vhdl-200x@eda.org [mailto:owner-vhdl-200x@eda.org] On Behalf Of Jim Lewis
> Sent: Monday, March 10, 2014 6:41 PM
> To: vhdl-200x@eda.org
> Subject: Re: [vhdl-200x] Switch model
>
> HI Jakko,
>
> I would particularly be interested in seeing an example and hardware picture of something that requires conditional usage of this.
>
> I would more likely call it a switch or attachment operation. Calling it an assignment is going to make people want to inject delta cycles - which is not going to work.
>
> Jim
>
> > Hi Brent,
>
> >
>
> >
>
> > What you actually want is a bidirectional assignment (for any resolved type).
>
> >
>
> > The problem with the code you listed below, is that you cannot have 2 of those assignments in a row, it will lead to wrong results.
>
> >
>
> > If you could assign 2 ways (like tran or tranif), then the problem is solved.
>
> >
>
> > I'd like to see something like
>
> >
>
> > a <=> b [when c else 'Z'];
>
> >
>
> > This would ease multiport wires with bidirectional (and conditional) assignments.
>
> >
>
> > Jakko
>
> --
>
> ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
>
> Jim Lewis
>
> VHDL Training Expert, SynthWorks
>
> IEEE 1076 VHDL Working Group Chair
>
> Open Source VHDL Verification Methodology (OSVVM), Chief Architect and Co-founder
>
> 1-503-320-0782
>
> Jim@SynthWorks.com <mailto:Jim@SynthWorks.com>
>
> http://www.SynthWorks.com
>
> VHDL Training on leading-edge, best coding practices for hardware design and verification.
>
> ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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-- 
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Jim Lewis
VHDL Training Expert, SynthWorks
IEEE 1076 VHDL Working Group Chair
Open Source VHDL Verification Methodology (OSVVM), Chief Architect and Co-founder

1-503-320-0782
Jim@SynthWorks.com
http://www.SynthWorks.com

VHDL Training on leading-edge, best coding practices for hardware design and verification.
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~


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