Hi Rick, Would have been happy to support your detailed proposal for this for VHDL-2008. However, while people asked for the feature, no one liked it so much that they were willing to volunteer to write it up and make it happen. I suspect the rest of the working group would have supported this work also if someone who really needed it would have written the proposal. I would be happy to support it now too. We need to quantify exactly what we need. I understand connections of the form: A <=> B ; A <=> B when S = '1' ; However, VHDL-2008 had requests for something of the form without any circuit for it. I have never had a need for this, so this meant to me that I did not understand what was wanted enough to successfully complete a proposal. A <=> B when S = '1' else C ; Can anyone provide a compelling reason (circuit not words) to implement this? We need a proposal documenting all forms needed and the compelling reason (circuits not words) to implement it. Jim > Jim, > > Pull up the datasheet for a TI SN74CBT3125D. I have been asking for > this since the late 1990s. > > Rick > > > > On 03/10/2014 07:41 PM, Jim Lewis wrote: >> HI Jakko, >> I would particularly be interested in seeing an example and hardware >> picture of something that requires conditional usage of this. >> >> I would more likely call it a switch or attachment operation. Calling it >> an assignment is going to make people want to inject delta cycles - >> which is not going to work. >> >> Jim >> >> >> >>> Hi Brent, >>> >>> >>> What you actually want is a bidirectional assignment (for any resolved >>> type). >>> >>> The problem with the code you listed below, is that you cannot have 2 >>> of those assignments in a row, it will lead to wrong results. >>> >>> If you could assign 2 ways (like tran or tranif), then the problem is >>> solved. >>> >>> I'd like to see something like >>> >>> a <=> b [when c else 'Z']; >>> >>> This would ease multiport wires with bidirectional (and conditional) >>> assignments. >>> >>> Jakko >> -- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Jim Lewis VHDL Training Expert, SynthWorks IEEE 1076 VHDL Working Group Chair Open Source VHDL Verification Methodology (OSVVM), Chief Architect and Co-founder 1-503-320-0782 Jim@SynthWorks.com http://www.SynthWorks.com VHDL Training on leading-edge, best coding practices for hardware design and verification. ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean.Received on Mon Mar 10 13:36:33 2014
This archive was generated by hypermail 2.1.8 : Mon Mar 10 2014 - 13:36:46 PDT