RE: [vhdl-200x] FSM safe design

My understanding is that the problem goes much further than just non-power-of-two state counts.

Even if you have (for example) 4 states in your state machine, the tools will (often) pick an encoding with redundant states.  Especially in FPGA-land, where one-hot encoding is popular for efficiency reasons, a 4-state FSM would have 4 flipflops, and therefore 12 "redundant" (and unpredictably behaved) states!

I agree that a well-defined standard attribute would be useful to handle this behaviour, as the two synthesisers I am familiar with (XST and Synplify) currently operate in different ways.

XST has 

  attribute safe_implementation of
      entity_name|component_name|signal_name}:entity|component|signal is "{yes|no}}";

along with 
  attribute safe_recovery_state: string; 

for when you need control over which state to "recover to". If unused, XST will include logic to return to the reset (or startup, if no reset logic is present) state if any undefined states are entered.

Synplify offers:
   attribute syn_safe_case of architectureName : architecture is TRUE;

along with separate error monitoring functionality

and
   attribute syn_fsm_correction of architectureName : architecture is "hamming3";

which provides single bit error correction.

The only overlap there is the function to provide a "safe" encoding, but the mitigation actions are also different between the tools.  

My current feeling is that an XST-like approach (where safe-encodings are produced along with a defined return to a particular state) would be a useful standardised functionality, vendors are still free to provide further attributes for more complex functions.

Cheers,
Martin

-- 
Martin Thompson BEng(Hons) MIET CEng
TRW Conekt, Stratford Road, Solihull, B90 4GW
martin.j.thompson@trw.com  +44 121 627 3569  
http://www.conekt.co.uk/

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