Re: EXTERNAL: Re: [vhdl-200x] Sizing of variables and signals from initial values

Hi,
> I do exactly what you suggest: declare sizer constants, then use their
> 'subtype to declare the signals I want.  The whole point of my original
> question is that I don't see the need for this two-step process.  Let's
> allow sizing of variables and signals from expressions, then it's only a
> one-step process.

I think we should also consider getting 'range to work on a return value
of an expression, so that the following would work:
   entity e is
   port (
     B, C : in ufixed(7 downto -4) ;
     . . .
   ) ;
   end entity E ;
   architecture A of e is
     signal A : ufixed( (B + C)'range ) ;
   begin

It would have helped some of the resizing if 'range was a
first class object and we could return a range from a function.

> It's not hard to define the mixed arithmetic (at least most of it).  I
> have a few suggestions for numeric_std types at
> [http://www.eda-twiki.org/cgi-bin/view.cgi/P1076/StandardPackages#numeric_st
> d_Additions].  Jim pointed out that the mixed arithmetic for
> signed/unsigned makes it hard to use literals in expressions (e.g. a +
> "1010") since the literal type is ambiguous.  I do it anyway because I
> don't use literals in that way -- or I qualify them if I do use them.
> (Personally, I think it's "evil" to *not* qualify signed/unsigned
> literals.)

Yea, I am particular about a type having a literal
that works with a type in simple expressions.

For mixing two types, you really should have a type qualifier
designating the type change.   Isn't there a to_sfixed that
takes care of the resizing of a ufixed object.

Best,
Jim
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Jim Lewis
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SynthWorks Design Inc.           http://www.SynthWorks.com
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