RE: EXTERNAL: Re: [vhdl-200x] Sizing of variables and signals from initial values

Andy:

I do exactly what you suggest: declare sizer constants, then use their
'subtype to declare the signals I want.  The whole point of my original
question is that I don't see the need for this two-step process.  Let's
allow sizing of variables and signals from expressions, then it's only a
one-step process. 

It's not hard to define the mixed arithmetic (at least most of it).  I
have a few suggestions for numeric_std types at
[http://www.eda-twiki.org/cgi-bin/view.cgi/P1076/StandardPackages#numeric_st
d_Additions].  Jim pointed out that the mixed arithmetic for
signed/unsigned makes it hard to use literals in expressions (e.g. a +
"1010") since the literal type is ambiguous.  I do it anyway because I
don't use literals in that way -- or I qualify them if I do use them.
(Personally, I think it's "evil" to *not* qualify signed/unsigned
literals.)

For fixed-point math, literals are out of the question because you can't
set the bit range on a literal.  So mixed arithmetic there shouldn't
have any problems.  Feel free to add what you want to the page I
referenced.  I haven't yet added my fixed_pkg wish list, so it's a blank
slate at the moment.

Enjoy!

- Ryan

-----Original Message-----
From: owner-vhdl-200x@eda.org [mailto:owner-vhdl-200x@eda.org] On Behalf
Of Jones, Andy D
Sent: Wednesday, April 24, 2013 5:47 PM
To: vhdl-200x@eda.org
Subject: RE: EXTERNAL: Re: [vhdl-200x] Sizing of variables and signals
from initial values

David,

I agree whole-heartedly with the "lossless" theory of operations (except
for division). I sometimes use ufixed instead of unsigned just because
of the lossless arithmetic* when integers won't handle the range.

While in vhdl-2008 I can declare constants using the initialization
expression to set the range, I cannot do that with variable/signal
declarations.  You can however declare "sizer" constants this way, and
then use their ranges to declare the variables/signals. Just a little
more verbose...

I don't really think there is a better way to do it with functions than
what you did, and the packages as a whole are fundamental game-changers
for VHDL synthesis. Not even SV can do that!

*I only wish there was a seamless way to make ufixed subtraction expand
to sfixed, and handle mixed sfixed/ufixed arithmetic in a clean yet
reasonable way. I often use the (natural - 1 < 0) trick to catch the
carry/borrow on down-counters.

Andy D Jones
Electrical Engineering
Lockheed Martin Missiles and Fire Control
Dallas TX





-----Original Message-----
From: owner-vhdl-200x@eda.org [mailto:owner-vhdl-200x@eda.org] On Behalf
Of David Bishop
Sent: Wednesday, April 24, 2013 4:00 PM
To: vhdl-200x@eda.org
Subject: Re: EXTERNAL: Re: [vhdl-200x] Sizing of variables and signals
from initial values

On 04/24/2013 03:02 PM, Jones, Andy D wrote:
> Formatting error... example should be:
>
> Variable a, b : ufixed(arg'range) := (others => '0'); -- 0.0
>
> Variable sum : ufixed := a + b; -- also 0.0, but "bigger"
>
> Variable product : ufixed := a * b; -- still 0.0, but even "bigger"
>
Cleaver.  This will work to bound the types.

I admit the helper scripts here are a bit verbose, but I could not think

of a better way to do it.   The idea here is that none of the operations

do any rounding, they just let the number grow.   The way I fix this 
issue is like this:

variable a, b : ufixed (arg'range);
variable result : ufixed (arg'range);

result := resize ((a + b) * a, result'high, result'low);


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