RE: EXTERNAL: Re: [vhdl-200x] Sizing of variables and signals from initial values

Andy:

David Bishop and I discussed this.  In fact, the initial values are
*not* needed.  The size of the result is independent of the values of
the operand.  Of course, if you want one of those variables to have a
valid initial value, then its dependencies will also need to have valid
initial values.

In fact, as of VHDL-2008, this approach works with output ports as well.
In the bad-old VHDL-93 days, you could get the attributes of an output
port but not its value.  So we could use data_out'range but not data_out
+ b.

I agree, the helper functions here are verbose at best.  They do help,
but it's a lot of extra code.

- Ryan

-----Original Message-----
From: owner-vhdl-200x@eda.org [mailto:owner-vhdl-200x@eda.org] On Behalf
Of Jones, Andy D
Sent: Wednesday, April 24, 2013 1:02 PM
To: vhdl-200x@eda.org
Subject: RE: EXTERNAL: Re: [vhdl-200x] Sizing of variables and signals
from initial values

Formatting error... example should be:

Variable a, b : ufixed(arg'range) := (others => '0'); -- 0.0 

Variable sum : ufixed := a + b; -- also 0.0, but "bigger"

Variable product : ufixed := a * b; -- still 0.0, but even "bigger"

Andy

-----Original Message-----
From: owner-vhdl-200x@eda.org [mailto:owner-vhdl-200x@eda.org] On Behalf
Of Jones, Andy D
Sent: Wednesday, April 24, 2013 1:50 PM
To: vhdl-200x@eda.org
Subject: RE: EXTERNAL: Re: [vhdl-200x] Sizing of variables and signals
from initial values

Yes, I have run into exactly the same issue when using fixed point!

But in my case, to be able to use such a capability effectively, the
initial values of other non-constant objects would have to be available
as well. (I'm not sure they are if in the same declarative region).

Variable a, b : ufixed(arg'range) := (others => '0'); -- 0.0 Variable
sum : ufixed := a + b; -- also 0.0, but "bigger"
Variable product := ufixed := a * b; -- still 0.0, but even "bigger"

I know, there are functions that can be used for this, but they're ugly
(IMHO).

Andy D Jones
Electrical Engineering
Lockheed Martin Missiles and Fire Control Dallas TX





-----Original Message-----
From: owner-vhdl-200x@eda.org [mailto:owner-vhdl-200x@eda.org] On Behalf
Of Jim Lewis
Sent: Wednesday, April 24, 2013 12:31 PM
To: vhdl-200x@eda.org
Subject: EXTERNAL: Re: [vhdl-200x] Sizing of variables and signals from
initial values

Particularly curious as the following is ok:
constant MY_SLV : std_logic_vector := "0011" ; signal MySlvSig :
std_logic_vector(MY_SLV'range) ;

Jim

> Is there any reason that constants can get their array range 
> constraints from initial values, but variables and signals can't?  (I 
> believe these rules are standardized, but I'm looking for the 
> reasoning behind the
> standard.)  Allowing the latter would make fixed-point design easier.
>
> Thanks!
>
> ---
> Ryan Hinton
> L-3 Communications / Communication Systems West 
> ryan.w.hinton@L-3com.com
>
>
>


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