RE: EXTERNAL: Re: [vhdl-200x] Sizing of variables and signals from initial values

From: Jones, Andy D <andy.d.jones@lmco.com>
Date: Wed Apr 24 2013 - 12:02:07 PDT
Formatting error... example should be:

Variable a, b : ufixed(arg'range) := (others => '0'); -- 0.0 

Variable sum : ufixed := a + b; -- also 0.0, but "bigger"

Variable product : ufixed := a * b; -- still 0.0, but even "bigger"

Andy

-----Original Message-----
From: owner-vhdl-200x@eda.org [mailto:owner-vhdl-200x@eda.org] On Behalf Of Jones, Andy D
Sent: Wednesday, April 24, 2013 1:50 PM
To: vhdl-200x@eda.org
Subject: RE: EXTERNAL: Re: [vhdl-200x] Sizing of variables and signals from initial values

Yes, I have run into exactly the same issue when using fixed point!

But in my case, to be able to use such a capability effectively, the initial values of other non-constant objects would have to be available as well. (I'm not sure they are if in the same declarative region).

Variable a, b : ufixed(arg'range) := (others => '0'); -- 0.0 Variable sum : ufixed := a + b; -- also 0.0, but "bigger"
Variable product := ufixed := a * b; -- still 0.0, but even "bigger"

I know, there are functions that can be used for this, but they're ugly (IMHO).

Andy D Jones
Electrical Engineering
Lockheed Martin Missiles and Fire Control Dallas TX





-----Original Message-----
From: owner-vhdl-200x@eda.org [mailto:owner-vhdl-200x@eda.org] On Behalf Of Jim Lewis
Sent: Wednesday, April 24, 2013 12:31 PM
To: vhdl-200x@eda.org
Subject: EXTERNAL: Re: [vhdl-200x] Sizing of variables and signals from initial values

Particularly curious as the following is ok:
constant MY_SLV : std_logic_vector := "0011" ; signal MySlvSig : std_logic_vector(MY_SLV'range) ;

Jim

> Is there any reason that constants can get their array range 
> constraints from initial values, but variables and signals can't?  (I 
> believe these rules are standardized, but I'm looking for the 
> reasoning behind the
> standard.)  Allowing the latter would make fixed-point design easier.
>
> Thanks!
>
> ---
> Ryan Hinton
> L-3 Communications / Communication Systems West 
> ryan.w.hinton@L-3com.com
>
>
>


--
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Jim Lewis
Director of Training             mailto:Jim@SynthWorks.com
SynthWorks Design Inc.           http://www.SynthWorks.com
1-503-320-0782

Expert VHDL training with a focus on hardware design and test.
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

--
This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean.


--
This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean.



-- 
This message has been scanned for viruses and
dangerous content by MailScanner, and is
believed to be clean.
Received on Wed Apr 24 12:03:15 2013

This archive was generated by hypermail 2.1.8 : Wed Apr 24 2013 - 12:03:20 PDT