RE: EXTERNAL: [vhdl-200x] VHDL ternary operation

An inline operator and "clear intent," especially at first glance, are mutually exclusive, in my opinion.

Andy

From: owner-vhdl-200x@eda.org [mailto:owner-vhdl-200x@eda.org] On Behalf Of Daniel Kho
Sent: Friday, March 29, 2013 8:34 PM
To: vhdl-200x@eda.org
Subject: Re: EXTERNAL: [vhdl-200x] VHDL ternary operation

Thanks Jim, Mike, and Andy.
Yes, I could write a function, though I still hope that there's something I could use out-of-the-box from the standard.
I like that "function with anonymous types" idea. So I could write:
cond(fault,"pass","fail");

However, I was also thinking of using inline operators (so that at first glance, the intent becomes clear).
Have we in the past explored the possibility of introducing inline ternary operators (similar to Verilog)?
fault ? "pass" : "fail"
or at least something like:
fault ? ("pass", "fail")
where the "function with anonymous type" could be defined as:
function "?"(sel:boolean; t,f: anonymous) return anonymous;
and could be a generic subprogram.

Perhaps even the following makes sense:
function "?"(sel:boolean; din_vectors: anonymous_vector) return anonymous;

So we could use it like this:
fault ? ("pass", "fail")

As was mentioned, when-else can only be used for conditional assignments, which I feel is too limiting. Can its use be extended to expressions as well (how feasible is it for a tool vendor)?

Or perhaps we could explore (or re-explore) the possibility of having inline ternary operators that can be used in many ways, including conditional assignments and expressions.
Just my 2 cents.

regards, daniel

On 29 March 2013 23:48, Mike Treseler <mtreseler@gmail.com<mailto:mtreseler@gmail.com>> wrote:
On Thu, Mar 28, 2013 at 7:40 AM, Jones, Andy D <andy.d.jones@lmco.com<mailto:andy.d.jones@lmco.com>> wrote:
> Daniel,
>
>
>
> "pass" when fault else "fail" is NOT an expression. It is the RHS of a
> conditional assignment statement. Such a RHS may contain expressions, but
> expressions may not contain a conditional assignment RHS.
>
>
>
> Since conditional assignments can be open-ended, in effect meaning that the
> assignment does not occur if no "when" expression evaluates as true, its use
> as an expression is not possible.
>
>
>
> To solve your immediate problem, you could write a function that takes a
> boolean argument and returns "pass" or "fail" strings, or you could create a
> constant array of two strings, indexed by boolean, e.g. (true => "fail",
> false => "pass"). Then you could include the function call or constant in
> your report expression.
It's a hard problem. 'Just write function' is good advice. -- MT

------------------------------------------------------------------------------
   function sel (                                  -- sel(false,a,b) => a
      choice : boolean;                         -- sel( true,a,b) => b
      t, f   : std_logic_vector)                -- works like  "arg ? a:b"
      return std_logic_vector
   is
   begin
      if choice then return t; else return f; end if;
   end function sel;

------------------------------------------------------------------------------
   function push (                        -- Push byte into word, uses sel()
      byte       : in std_logic_vector;
      word       : in std_logic_vector;
      shift_left : in boolean := true)  -- left is default
      return std_logic_vector
   is  -- push byte into word from left or right
      variable byte_v :  std_logic_vector(byte'length-1 downto 0) := byte;
      variable word_v : std_logic_vector(word'length-1 downto 0) := word;
   begin
      return(
         sel(                    -- select value for true or false
            choice => shift_left,
            t =>              word_v(word_v'left - byte'length downto
0) & byte_v,
            f => byte_v & word_v(word_v'left     downto byte'length))
         );
   end function push;
>
>
> Andy
>
>
>
> From: owner-vhdl-200x@eda.org<mailto:owner-vhdl-200x@eda.org> [mailto:owner-vhdl-200x@eda.org<mailto:owner-vhdl-200x@eda.org>] On Behalf Of
> Daniel Kho
> Sent: Thursday, March 28, 2013 4:19 AM
> To: vhdl-200x@eda.org<mailto:vhdl-200x@eda.org>
> Subject: EXTERNAL: [vhdl-200x] VHDL ternary operation
>
>
>
> Hi all,
>
> I'm wondering if the current revision supports something like the following?
>
> report to_hstring(index) & ", " & ("pass" when fault else "fail") & lf &
> nul;
>
> where "index" is an unsigned vector, and "fault" is a boolean.
>
>
>
> The expression ("pass" when fault else "fail") can already be used directly
> in clocked processes, but I'm not too sure if the standard allows this to be
> used within report statements.
>
> If there's a better way of writing which could produce the same effect, do
> share with me as well.
>
>
>
> regards, daniel
>
>
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