[vhdl-200x] Expression signal assertion

Whilst scavenging through some of the older reflector Emails, I stumbled
upon Jim's original 'wish list' document for the VHDL2008 (eventual) fast
track stuff:

    http://www.eda-twiki.org/vhdl-200x/docs/jims_200x_requests.pdf

In section 10.1, I saw:

    Y => signal'(A and B),

for a port mapping and thought what a nice idea.

Does anyone know if this was pursued/rejected, and if not/so then why-not/why?


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Regards,

         Brent Hayhoe.

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