Re: [vhdl-200x] Expression signal assertion

Brent,

VHDL 2008 did it a little bit differently: it allows expression preceded by
'inertial' keyword as the actual associated with input port formal  in a
port map.
Such association implies the use of anonymous signal to which the
expression value is assigned concurrently; the anonymous signal is them
mapped to the formal port.
So you can write:
    P => inertial A and B
which will be translated internally to:
-- outside the instantiation
    anonymous <= A and B;
-- within port map
    P => anonymous
The big bonus is that in case of non-static expression being mapped to
port, 'inertial' is automatically assumed, so you can, but do not have to
write it.
So in our case - if P is bit input port and A and B are bit signals - you
can write:
    P => A and B
and it will still create that anonymous intermediate signal and concurrent
assignment to it.
Of course in both cases one delta cycle is added during simulation due to
the concurrent assignment to the signal.
If you have access to the 2008 standard, everything is described in
clause 6.5.6.3.

Thank you,

Jerry Kaczynski
Aldec research Engineer


On Tue, Feb 12, 2013 at 3:27 PM, Brent Hayhoe <Brent.Hayhoe@aftonroy.com>wrote:

> Whilst scavenging through some of the older reflector Emails, I stumbled
> upon Jim's original 'wish list' document for the VHDL2008 (eventual) fast
> track stuff:
>
>    http://www.eda-twiki.org/vhdl-200x/**docs/jims_200x_requests.pdf<http://www.eda-twiki.org/vhdl-200x/docs/jims_200x_requests.pdf>
>
> In section 10.1, I saw:
>
>    Y => signal'(A and B),
>
> for a port mapping and thought what a nice idea.
>
> Does anyone know if this was pursued/rejected, and if not/so then
> why-not/why?
>
>
> --
>
> Regards,
>
>         Brent Hayhoe.
>
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