Hi Matthias, I use stop. I have a set of text extensions in a package. One of them is EndStatus shown below. Best, Jim ------------------------------------------------------------ procedure EndStatus ( -- If ErrCnt = 0 print success message and stop simulation -- If ErrCnt /= 0 print failure message and stop simulation ------------------------------------------------------------ ErrCnt : In integer ; MSG : In string := "Test" ; StopSim : In boolean := TRUE ) is begin write(output, LF & LF) ; -- Print 2 blank lines if (ErrCnt = 0) then -- passed write(output, "%%DONE " & MSG & " Passed at time: " & to_string(NOW) & LF & LF) ; if StopSim then std.env.stop ; end if ; else -- failed write(output, "%%DONE " & MSG & " Failed." & " Total Error(s) = " & integer'image(ErrCnt) & LF & LF) ; if StopSim then std.env.stop ; end if ; end if ; wait ; -- stop this thread here if StopSim is FALSE end procedure ; > SV has the "final" procedure that does something that you requested. From 1800: > 9.2.3 Final procedures > The final procedure is like an initial procedure, defining a procedural block of statements, except that > it occurs at the end of simulation time and executes without delays. A final procedure is typically used to > display statistical information about the simulation. > The only statements allowed inside a final procedure are those permitted inside a function declaration, so > that they execute within a single simulation cycle. Unlike an initial procedure, the final procedure does > not execute as a separate process; instead, it executes in zero time, as a series of function calls from a single > process. All final procedures shall execute in an arbitrary order. No remaining scheduled events shall exe- > cute after all final procedures have executed. > A final procedure executes when simulation ends due to an explicit or implicit call to $finish. > final > begin > $display("Number of cycles executed %d",$time/period); > $display("Final PC = %h",PC); > end > Execution of $finish, tf_dofinish(), or vpi_control(vpiFinish,...) from within a final pro- > cedure shall cause the simulation to end immediately. A final procedure can only trigger once in a simula- > tion. > A final procedure shall execute before any PLI callbacks that indicate the end of simulation. > SystemVerilog final procedures execute in an arbitrary but deterministic sequential order. This is possible > because final procedures are limited to the legal set of statements allowed for functions. > NOTE—SystemVerilog does not specify the ordering in which final procedures are executed, but implementations > should define rules that preserve the ordering between runs. This helps keep the output log file stable because final > procedures are mainly used for displaying statistics." > > If not yet defined, perhaps VHDL 200x needs to have something similar to that. > Ben Cohen systemverilog.us <http://systemverilog.us> > > On Wed, Feb 6, 2013 at 3:32 AM, Matthias Alles <matthias.alles@creonic.com <mailto:matthias.alles@creonic.com>> wrote: > > Hi all, > > I recently experimented with the finish call within the std.env package > that is new in VHDL-2008. > > When I call "finish" within my testbench I get four lines of output (at > least for Aldec's RivieraPro) that follow my custom message: > > -> Here comes my custom message! > # RUNTIME: Info: RUNTIME_0142 tb_x.vhd (433): finish called. > # KERNEL: Time: 253825 ns, Iteration: 1, Instance: /tb_x, Process: > pr_compare_out. > # KERNEL: stopped at time: 253825 ns > # VSIM: Simulation has finished. There are no more test vectors to simulate. > > In the last line the simulator gives some message that wasn't defined by > me and probably doesn't make sense for my situation. I would prefer to > read something: x cases simulated with y errors. > > Wouldn't it be nice to have the stop and finish calls also with a string > as parameter so that I could define my custom message that would pop up > as the last statement? I wouldn't need to look through all the messages > above as they don't interest me in detail, and furthermore the simulator > wouldn't need define a string on its own that isn't always appropriate. > > So what do you think? Shouldn't be hard to implement.. > > Thanks, > Matthias > > -- > This message has been scanned for viruses and > dangerous content by MailScanner, and is > believed to be clean. > > > > -- > This message has been scanned for viruses and > dangerous content by *MailScanner* <http://www.mailscanner.info/>, and is > believed to be clean. -- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Jim Lewis Director of Training mailto:Jim@SynthWorks.com SynthWorks Design Inc. http://www.SynthWorks.com 1-503-590-4787 Expert VHDL Training for Hardware Design and Verification ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean.Received on Wed Feb 6 08:33:43 2013
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