RE: [vhdl-200x] Improved std.env package?

I was recently doing some work that involved comparing the runtime of
alternative VHDL models.

So this is a useful feature.   It would not be used all that often but the
capability is sometimes needed.

There is no affect when not used.

 

Joanne

 

From: owner-vhdl-200x@eda.org [mailto:owner-vhdl-200x@eda.org] On Behalf Of
Ben Cohen
Sent: Wednesday, February 06, 2013 9:28 AM
To: vhdl-200x@eda.org
Subject: Re: [vhdl-200x] Improved std.env package?

 

SV has the "final" procedure that does something that you requested.  From
1800: 

9.2.3 Final procedures

The final procedure is like an initial procedure, defining a procedural
block of statements, except that

it occurs at the end of simulation time and executes without delays. A final
procedure is typically used to

display statistical information about the simulation.

The only statements allowed inside a final procedure are those permitted
inside a function declaration, so

that they execute within a single simulation cycle. Unlike an initial
procedure, the final procedure does

not execute as a separate process; instead, it executes in zero time, as a
series of function calls from a single

process. All final procedures shall execute in an arbitrary order. No
remaining scheduled events shall exe-

cute after all final procedures have executed.

A final procedure executes when simulation ends due to an explicit or
implicit call to $finish.

final

begin

  $display("Number of cycles executed %d",$time/period);

  $display("Final PC = %h",PC);

end

Execution of $finish, tf_dofinish(), or vpi_control(vpiFinish,...) from
within a final pro-

cedure shall cause the simulation to end immediately. A final procedure can
only trigger once in a simula-

tion.

A final procedure shall execute before any PLI callbacks that indicate the
end of simulation.

SystemVerilog final procedures execute in an arbitrary but deterministic
sequential order. This is possible

because final procedures are limited to the legal set of statements allowed
for functions.

NOTE-SystemVerilog does not specify the ordering in which final procedures
are executed, but implementations

should define rules that preserve the ordering between runs. This helps keep
the output log file stable because final

procedures are mainly used for displaying statistics."

 

If not yet defined, perhaps VHDL 200x needs to have something similar to
that.

Ben Cohen systemverilog.us

 

On Wed, Feb 6, 2013 at 3:32 AM, Matthias Alles <matthias.alles@creonic.com>
wrote:

Hi all,

I recently experimented with the finish call within the std.env package
that is new in VHDL-2008.

When I call "finish" within my testbench I get four lines of output (at
least for Aldec's RivieraPro) that follow my custom message:

-> Here comes my custom message!
# RUNTIME: Info: RUNTIME_0142 tb_x.vhd (433): finish called.
# KERNEL: Time: 253825 ns,  Iteration: 1,  Instance: /tb_x,  Process:
pr_compare_out.
# KERNEL: stopped at time: 253825 ns
# VSIM: Simulation has finished. There are no more test vectors to simulate.

In the last line the simulator gives some message that wasn't defined by
me and probably doesn't make sense for my situation. I would prefer to
read something: x cases simulated with y errors.

Wouldn't it be nice to have the stop and finish calls also with a string
as parameter so that I could define my custom message that would pop up
as the last statement? I wouldn't need to look through all the messages
above as they don't interest me in detail, and furthermore the simulator
wouldn't need define a string on its own that isn't always appropriate.

So what do you think? Shouldn't be hard to implement..

Thanks,
Matthias

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