Hi all, I recently experimented with the finish call within the std.env package that is new in VHDL-2008. When I call "finish" within my testbench I get four lines of output (at least for Aldec's RivieraPro) that follow my custom message: -> Here comes my custom message! # RUNTIME: Info: RUNTIME_0142 tb_x.vhd (433): finish called. # KERNEL: Time: 253825 ns, Iteration: 1, Instance: /tb_x, Process: pr_compare_out. # KERNEL: stopped at time: 253825 ns # VSIM: Simulation has finished. There are no more test vectors to simulate. In the last line the simulator gives some message that wasn't defined by me and probably doesn't make sense for my situation. I would prefer to read something: x cases simulated with y errors. Wouldn't it be nice to have the stop and finish calls also with a string as parameter so that I could define my custom message that would pop up as the last statement? I wouldn't need to look through all the messages above as they don't interest me in detail, and furthermore the simulator wouldn't need define a string on its own that isn't always appropriate. So what do you think? Shouldn't be hard to implement.. Thanks, Matthias -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean.Received on Wed Feb 6 03:33:13 2013
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