Hi Brent, A use case that illustrates what your are trying to do and why would be helpful. I am using protected types quite extensively, but I suspect that I am using them for a different purpose than you. Most of my shared variable declarations I use are private to an instance of a design and I declare them in the architecture declaration region. Are you putting the shared variable declarations in a package to allow different instances (perhaps of the same design) to share a data structure? Currently I am more limited by not allowing shared variables on interfaces and not allowing arrays of shared variables. I also need generics on protected types so I can effect an initializer. Best, Jim > Hi everyone, > > I was just reading through Peter Ashenden's analysis of the VHDL2008 IR 2119: > > http://www.eda-twiki.org/isac/IRs-VHDL-2002/IR2119.txt > > and was surprised that to see that there wasn't more support for this. > > I know it caught me out in the same way as the proposer described and at around the same time. Maybe users hadn't gotten around to using shared variables because of the (perceived) hassle of declaring > protected types and thus the lack of support for this proposal. I know a lot of users that I come across still find them (protected types) a bit 'mind bending' at first. > > It's something that hassles me in my verification jobs a lot and so I thought that I'd resurrect the issue again, so comments please: > > http://www.eda-twiki.org/cgi-bin/view.cgi/Sandbox/DeferredSharedVariables > > > Thanks in advance. > -- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Jim Lewis Director of Training mailto:Jim@SynthWorks.com SynthWorks Design Inc. http://www.SynthWorks.com 1-503-590-4787 Expert VHDL Training for Hardware Design and Verification ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean.Received on Mon Dec 17 14:33:57 2012
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