Re: [vhdl-200x] Records with diectional subtypes

Hi Peter,

If we create a different 'single enable' record subtype, will we not have
problems at the top level, i.e. have to break the new record type out so as to
connect them to the existing subtypes? And isn't this something we're trying to
avoid?

Regards,

Brent Hayhoe

On 21/08/2012 15:39, Peter Flake wrote:
>
> Hi Brent,
>
> The subtype mechanism should not be used to do complex wiring to the slaves.
> Each slave has only one enable and does not "know" which element of the array
> it is.
>
> Since I do not see how to put this information in the port map, I think you
> have to create a different signal record instance (containing one enable) for
> each slave instance.
>
> I have edited the Twiki to include this point.
>
> Regards,
>
> Peter Flake
>
> *From:*owner-vhdl-200x@eda.org [mailto:owner-vhdl-200x@eda.org] *On Behalf Of
> *Brent Hayhoe
> *Sent:* 20 August 2012 19:28
> *To:* vhdl-200x@eda.org
> *Subject:* Re: [vhdl-200x] Records with diectional subtypes
>
> Hi Peter,
>
> I notice that Jim embedded his comments in the TWiki page. As I know not how
>
> to do this, nor given my verbosity, do I think that I should be allowed
>
> to ;-), I will limit myself to Emails.
>
> My question is embedded below:
>
> On 16/08/2012 21:07, Jim Lewis wrote:
>
> Hi Peter,
> In the Block Interface proposal, "Candidate: Records with diectional
> subtypes":
> http://www.eda-twiki.org/cgi-bin/view.cgi/P1076/BlockInterfaces#Candidate_Records_with_direction
>
>
> Can we extend this to also allow open in the subtype? The following slave
> does
> not use the "we" element (perhaps it is read only and never does a write):
>
> subtype t_slave is t_cpu_bus port(adr, dat, en : in; sdt, ack, err : out;
> we : open);
>
>
> Can we allow some ports to not use all elements?
>
> type t_cpu_bus is record
> adr : std_logic_vector(15 downto 0); --Address
> dat : std_logic_vector(15 downto 0); --Data from master to slave=
> we : std_logic; --Write enable from master=
> en : std_logic_(7 downto 0) ; --Enable from master=
> sdt : std_logic_vector(15 downto 0); --Data from slave to master=
> ack : std_logic; --Acknowledge from slave=
> err : std_logic; --Error from slave=
> end record;
>
> subtype t_master is t_cpu_bus port(adr, dat, we, en : out; sdt, ack, err :
> in);
>
> subtype t_slave is t_cpu_bus port(adr, dat, we, en(1) : in; sdt, ack, err
> : out ; en(7 downto 2), en(0) : open );
>
> So if I want to instantiate the full 8 slaves (as per your example) would I
> need 8 separate subtype declarations?
>
> subtype t_slave0 is t_cpu_bus port(adr, dat, we, en(0) : in; sdt, ack, err :
> out ; en(7 downto 1) : open );
>
> subtype t_slave1 is t_cpu_bus port(adr, dat, we, en(1) : in; sdt, ack, err :
> out ; en(7 downto 2), en(0) : open );
>
> ...
>
> subtype t_slave5 is t_cpu_bus port(adr, dat, we, en(5) : in; sdt, ack, err :
> out ; en(7 downto 6),
>
> en(4 downto 0) : open );
>
> ...
>
> subtype t_slave7 is t_cpu_bus port(adr, dat, we, en(7) : in; sdt, ack, err :
> out ; en(6 downto 0) : open );
>
> or have I misunderstood how this is to work?
>
>
> Inside the slave is en seen as en(1) or just en? Is there a notation
> that allows just en?
>
> All questions also on the twiki page.
>
> Best,
> Jim
>
>
>
>
> --
>
> Regards,
>
> Brent Hayhoe.
>
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-- 
Regards,
         Brent Hayhoe.
Aftonroy Limited                            Telephone: +44 (0)20-8449-1852
135 Lancaster Road,
New Barnet,                                    Mobile: +44 (0)79-6647-2574
Herts., EN4 8AJ,  U.K.                          Email: Brent.Hayhoe@Aftonroy.com
Registered Number: 1744190 England.
Registered Office:
4th Floor, Imperial House,
15 Kingsway,
London, WC2B 6UN, U.K.
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