Re: [vhdl-200x] Clocked Shorthand for Sequencing Testbench Assertions?

Hi Daniel,
That syntax is for assertions right? Are they
using it for testbench sequencing or randomizing
anything too?

The corresponding syntax for VHDL would be PSL in
the VHDL flavor.

> I'm still new to advanced VHDL verification techniques
You will probably need to read one of the PSL books.

Best,
Jim

> Hi all,
> I updated the Clocked Shorthand Wiki page with a question on whether it's currently possible to do VHDL testbench sequencing for property assertions, similar to what's been done in SV?
> For example, the SV sequence:
> d ##[1:3] e ##1 f;
>
> could perhaps follow the same clocked shorthand notation being currently proposed? For example, the above sequence could be written as follows in VHDL:
> seq := d, e @ (1 to 3), f @1;
>
> I'm still new to advanced VHDL verification techniques, so let me know if there is a compact way of defining test sequences using existing VHDL techniques.
>
> regards, daniel
>
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