[vhdl-200x] Clocked Shorthand for Sequencing Testbench Assertions?

From: Daniel Kho <daniel.kho@gmail.com>
Date: Sun Mar 11 2012 - 00:45:55 PST

Hi all,
I updated the Clocked Shorthand Wiki page with a question on whether it's
currently possible to do VHDL testbench sequencing for property assertions,
similar to what's been done in SV?
For example, the SV sequence:
    d ##[1:3] e ##1 f;

could perhaps follow the same clocked shorthand notation being currently
proposed? For example, the above sequence could be written as follows in
    seq := d, e @ (1 to 3), f @1;

I'm still new to advanced VHDL verification techniques, so let me know if
there is a compact way of defining test sequences using existing VHDL

regards, daniel

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Received on Sun Mar 11 00:46:43 2012

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