Re: [vhdl-200x] conditional compilation proposal

On 16/08/2011 13:46, john.aynsley@doulos.com wrote:
> Conditional compilation?
>
> One of the nice things about VHDL is its/relative/ orthogonality and
> economy of concept when compared with SystemVerilog. VHDL already has
> the generate statement. Before introducing conditional compilation, I
> would ask whether there is any use case for which it is really justified
> vs generate, and if so, whether generate could be extended to cover that
> case.

The problem with generate is that the code enclosed is analysed, and so
must be error-free. This is pretty much a requirement of any conditional
compilation construct that appears as part of the language itself.

The other issue is that generate can only appear within specific
sections of the source code. These two problems make it impossible to
use generate in any meaningful way except for generation itself.

Ok, there are many cases in which you can properly and cleanly work
around conditional inclusion, but there are equally many where you can't
- ignoring code which has bitrot, code under development, working around
compiler-specific bugs, and so on. It would also be very useful for
simple cases where VHDL already has a clean way of doing things -
selecting different vendor libraries, for example. How many engineers
will actually write a configuration to do this? In real life, not many,
I think.

It's easy to put forward theoretical arguments to dismiss
pre-processing, but I wonder how many of the people who do this actually
write code for a living. We're not doing anyone any favours by forcing
users to conform to a computer scientist's view of how best to do
things. Users already pre-process, in non-standard ways. This is an
opportunity to get the required functionality into tools, in a way that
doesn't impact on the language itself, by moving it into a separate (and
potentially optional) pre-processing phase.

-Evan

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