RE: [vhdl-200x] conditional compilation proposal

Hi,

From my experience with VHDL as a user, this is a very welcome feature.
However, from a vendor's perspective, I would hate to see this go the
text-munging way of something like cpp. Development tools that provide
real-time analysis of source code rely on the ability to parse the source
without text preprocessing. If conditional compilation directives can be
placed in arbitrary locations then you would lose that ability to easily do
real-time VHDL analysis.

I'm not sure what the motivation is behind the requirement "an independent
mechanism that should not have knowledge of the vhdl grammar and semantics
except to avoid fundamental conflicts in syntax" It seems that the end goal
can be achieved without requiring a separate preprocessing step and without
breaking the language grammar.

I also find that preprocessing that allows the user to construct text in
arbitrary ways just leads to code that is ugly and difficult to read.

A clean approach that would not require textual manipulation and maintain
readability, would be to allow conditional compilation directives to appear
between declarations and statements.

--Scott Thibault

Green Mountain Computing Systems, Inc.

www.gmvhdl.com

From: owner-vhdl-200x@eda.org [mailto:owner-vhdl-200x@eda.org] On Behalf Of
Shields, John
Sent: Monday, August 15, 2011 9:40 PM
To: vhdl-200x@eda.org
Subject: [vhdl-200x] conditional compilation proposal

Hi,

I've added a definition of the conditional compilation requirement and an
initial proposal for it. Members with access can see it in the requirements
list at http://www.eda-twiki.org/cgi-bin/view.cgi/P1076/ConditionalCompilation

Thanks, John

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