Re: [vhdl-200x] conditional compilation proposal

On 16/08/2011 11:49, Martin.J Thompson wrote:

>> 8 - #error/#warning are not necessary but, for practical reasons, should
>> be provided. If you give the user a tool to analyse a set of conditions,
>> then you also have to supply a way to tell them if they've made an error:
>>
>> #if complex-condA
>> ...
>> #elif complex-condB
>> ...
>> #else
>> #error "problem - should never reach here, or user didn't define X, etc"
>> #endif
>
> Can't we just do
>
> report "problem" severity [fatal|error|warning|note];

There are a number of problems with this. The most important is that the
preprocessor would have no way to identify reports that were intended as
preprocessor directives, rather than as VHDL output statements - hence
the requirement for a '#' or somesuch. So, something like this wouldn't
work:

#else
...lots of VHDL code, which just happens to include a 'report'
report "preprocessor problem - user didn't define X"
#endif

There are also implementation issues:

- report/printf/etc are intended to produce compiled code, whereas
#error/etc are effectively commands for the tool to issue a diagnostic
or error

- the difficulty of enabling and disabling translation in a multi-stage
compiler, where the directive may be found way down inside the syntax
tree, and the tree will already exist by the time that you start
analysing the tree. This means that preprocessing is generally a
completely separate stage before the main translation begins, so you
can't have bits of real VHDL in there

>> 11 - grave accent??! Horrible. Looks and feels amateurish, for obvious
>> reasons.
>
> They're not obvious to me, could you elaborate?

Verilog. Amateurish because the back-tick has to precede anything to be
replaced, and it's small and not immediately obvious, not to mention the
easy confusion with VHDL's attribute apostrophe.

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