Re: [vhdl-200x] conditional compilation proposal

From: Martin.J Thompson <Martin.J.Thompson@trw.com>
Date: Tue Aug 16 2011 - 03:49:06 PDT

A few comments on the comments:

> 1 - you need to be careful about any rigorous alignment with a subset of
> the C preprocessor. It's badly defined, and it's easy to construct
> corner cases that behave differently on different preprocessors
>

Agree

> 8 - #error/#warning are not necessary but, for practical reasons, should
> be provided. If you give the user a tool to analyse a set of conditions,
> then you also have to supply a way to tell them if they've made an error:
>
> #if complex-condA
> ...
> #elif complex-condB
> ...
> #else
> #error "problem - should never reach here, or user didn't define X, etc"
> #endif

Can't we just do

report "problem" severity [fatal|error|warning|note];

as we currently do

>
> 9 - source file inclusion... why? You suggest it under 'features', but
> the thrust of the comments above (persistent state across file
> boundaries, etc) argues *against* source file inclusion. I think VHDL
> already has this covered - we have no concept of "include files", for
> example. Do you have a use case for file inclusion in mind?
>

I also feel that file inclusion is very non-VHDLish (for want of a better phrase)

> 11 - grave accent??! Horrible. Looks and feels amateurish, for obvious
> reasons.

They're not obvious to me, could you elaborate?

Just don't use # unless it's going to work pretty much the same as the C preprocessor. Once they see "#if...." people will make (possibly unwarranted) assumptions.

Cheers,
Martin

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Martin Thompson CEng MIET
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Received on Tue Aug 16 03:49:51 2011

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