Re: [vhdl-200x] Requirements to do verification

On Fri, Apr 22, 2011 at 10:36 AM, Ken Campbell <sckoarn@storm.ca> wrote:
...
> So, to improve the chances of cross employment and standardization for the
> future of verification people, I recommend a UVM methods implementation as
> a target for VHDL language enhancements.

It seems to me that Ben Cohen's feature list below could be covered using
existing VHDL standards. What is needed is a community working on the problem.

> As Jim said, VHDL is very capable and very much alive.  I have recently
> started a blog describing how to best use the VHDL test bench package I
> published.  This has increased the downloads from 1-3 per day to 4-7.  The
> blog is getting more attention than I thought it would and for me that is
> evidence that VHDL is very much alive.

I would suggest moving your open sources to github to make use of the built-in
collaboration tools.

    -- Mike Treseler

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