Re: [vhdl-200x] Why OOP vs Generics

From: Jim Lewis <>
Date: Tue Mar 29 2011 - 00:25:45 PDT

Hi Jon,
> I disagree; there are *some* verification tasks (notably modelling)
> that can be well and elegantly done in mainstream OO languages,
> but constrained-random and a few other things really demand a
> language that has some domain-specific features.
I have been using a procedural based randomization methodology.
To date, I have not found a verification problem that is a
too challenging for this methodology. Can you provide an
English language description for a verification problem
(meaning I am not interested in solving Sudoko) of something
that you think would be challenging.

> There's a "dream ticket" here, much undervalued in the industry
> but cherished by those in the know: VHDL for design, 'e' for
> verification.
Yuck. I am not interested in creating another Franken-language
like SystemVerilog?


Jim Lewis
Director of Training   
SynthWorks Design Inc. 
Expert VHDL Training for Hardware Design and Verification
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Received on Tue Mar 29 00:26:28 2011

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