Re: [vhdl-200x] VHDL enhancements wish list

On 2/24/2011 12:24 PM, ryan.w.hinton@L-3com.com wrote:
> David,
>
> This sounds scary and error-prone to me. With this approach I have to
> look all over the declarative regions inside and outside the entity (if
> the attribute is specified where the entity is instantiated) to find out
> what my clock is!

For most entities, I find that I use one clock and one reset. I would
find this short hand useful. I would, however, make sure that the
attribute section was just after my Architecture statement.

Should you forget to set these attributes, the Z-Transform with have to
error out.

> I much prefer a clocked process construct. The definition of this
> construct in the LRM should include some way of communicating the clock,
> reset, enable, etc. to operators within the process.

You could put the attributes on a single process, but if you went that
far, then the old "elsif rising_egde (clk)" would be shorter and easier
to understand.

I see this as a way to reduce the size of my code and make it more
understandable from an algorithmic point of view.

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