Re: [vhdl-200x] VHDL enhancements wish list

Hi Daniel,

>From: Daniel Kho
>Sent: Tuesday, February 22, 2011 1:06 AM
>To: vhdl-200x@eda.org
>Cc: Jim Lewis
>Subject: Re: [vhdl-200x] VHDL enhancements wish list
>Hi Jim,
>Use std_logic in conditionals (if (a) then ).
>[jim] Done in VHDL-2008 simplified conditionals
>Good one there. I'm still waiting for a tool that supports this.

>Just a few more (these aren't solely my suggestions; others have
>contributed to the discussion as well):
>1: make some currently non-synthesizable code become synthesizable.
>Examples are "after", "assert", "report", etc. Need to >study which of
>these are feasible to implement.

Some of them like assert are already supported by most synthesis tools. As
far as I know they only generate a warning rather than stopping the
synthesis process. I believe that synthesis vendors are already trying to
support as many language constructs as possible as this is a major product
differentiator.

>2: easier way to design configurable testbenches, e.g. support shorthand
>entity instantiation (to be embedded into >configurations) instead of
>component instantiation.

Please explain.

>3. Timing constraints supported by language.

This was mentioned before and I didn't understand it then, do you have an
example?

I know that synthesis tools supports all sorts of attributes to set pin
numbers, IOB's, fsm coding styles etc but I find it questionable coding
style as it makes your code highly un-portable.

Regards,
Hans
www.ht-lab.com

>
>..
>Regards,
>Daniel

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