Re: [vhdl-200x] VHDL enhancements wish list

Hi Jim,
* Use std_logic in conditionals (if (a) then ).
 [jim] Done in VHDL-2008 simplified conditionals*
Good one there. I'm still waiting for a tool that supports this.

Just a few more (these aren't solely my suggestions; others have contributed
to the discussion as well):
1: make some currently non-synthesizable code become synthesizable. Examples
are "after", "assert", "report", etc. Need to study which of these are
feasible to implement.

2: easier way to design configurable testbenches, e.g. support shorthand
entity instantiation (to be embedded into configurations) instead of
component instantiation.

3. Timing constraints supported by language.

*Let me throw out a general question, how do we move
to the next higher level of description where the
amount of pipelining is not known at the start of
the design and perhaps may be different for different
usages of the same block. Are generics effective?
Do we need a way for a synthesis tool to determine
this and feed it back to us?*

My guess is that pipelining info for a behavioural model will only be known
after at least 1 pass of synthesis/P&R. Current synthesis tools already have
ways to determine how many registers to insert to improve timing. But we
probably want to have more control over the number of pipeline stages that
gets synthesized - that's where generics (or others?) can come into play.
Other suggestions have been to use the "after" clause and "zt" function.
Maybe a combination of these would be good?

I'm thinking that we could use something like suggestion (3) to get the
synthesis tool to feedback some timing information on the design, and use it
to determine the optimal number of pipeline stages.

Regards,
Daniel

On Tue, Feb 22, 2011 at 6:42 AM, Jim Lewis <Jim@synthworks.com> wrote:

> All,
> It is really too early to talk about syntax of something
> other than to help sound out the requirements.
>
> _From Ryan I gathered_:
> I want a more concise way to specify flip-flops and pipelining.
>
> _From Ben, I gathered_:
> Having SystemVerilog-like syntax would be nice.
>
> _separate requests_
> Minimize package references.
> [jim] Done in VHDL-2008 context declarations
>
> Use std_logic in conditionals (if (a) then ).
> [jim] Done in VHDL-2008 simplified conditionals
>
> You can find the VHDL-2008 slides I shared with DASC at:
> http://www.synthworks.com/papers/vhdl_2008_DASC_s.pdf
>
> I will throw in a couple:
> For flip-flops, I would like to facilitate the re-use of
> intellectual property by having an abstraction that allows
> higher level changing of polarity of clock and reset, as
> well as, changing between asynchronous and synchronous
> reset.
>
> Let me throw out a general question, how do we move
> to the next higher level of description where the
> amount of pipelining is not known at the start of
> the design and perhaps may be different for different
> usages of the same block. Are generics effective?
> Do we need a way for a synthesis tool to determine
> this and feed it back to us?
>
> Some of the C synthesis tools seem to be taking blocks
> without flip-flops specified and adding them at
> appropriate places. Is this the future? Is there
> VHDL syntax that would simplify this process for the tools?
>
> Going back to the SystemVerilog. Always_ff,
> always_comb, always_lat assign logic intent to
> code and requires a simulator to check for basic
> hardware correctness. For me, a synthesis tool
> already does this (flags sensitivity list issues,
> reports warnings on latches and generally reports on
> the flipflops it creates). I don't need the simulator
> to do this too. In addition, if we assume "report
> all latches" (like a synthesis tool does), and adopt
> process(all) for combinational logic and use
> rising_edge/falling_edge for all flipflops,
> then the information is there - if only I am willing to
> pay for a vendor to implement the checks :).
>
>
> I think we need to keep talking about the requirements
> for flip-flop coding and agree upon them before we go
> forward and start worrying about the implementation.
>
>
> Best,
>
> Jim
> --
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> Director of Training mailto:Jim@SynthWorks.com
> SynthWorks Design Inc. http://www.SynthWorks.com
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>
> Expert VHDL Training for Hardware Design and Verification
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