Re: [vhdl-200x] VHDL enhancements wish list

From: Jim Lewis <>
Date: Fri Feb 18 2011 - 10:04:13 PST

Hi Ryan,
> 1. Shorthand for clocked process. It seems silly for an HDL to require
> coding conventions to describe 90+% of designs, namely clocked
> processes. Instead, (or in addition for the foreseeable future) VHDL
> could support something like the following.
> label: process clock(Clk) is
> -- declaration region for constants, variables, aliases, etc.
> synchronous reset(Rst)
> -- reset logic
> begin
> -- non-reset logic
> end process;

-- Are these ok?
AReg <= A when rising_edge(Clk) ; -- flip-flops
AReg <= Mux2(nReset, "0000", A) when rising_edge(Clk) ; -- synchronous reset
AReg <= "0000" when not nReset else A when rising_edge(Clk) ; -- asynchronous reset

I have also been thinking we need a standard set of RTL
procedures/functions that work as low level components:

AsyncReg(Clk, nReset, "0000", A, AReg) ;

Y <= Mux2(Sel, A, C) + Mux2(Sel, B, D) ;

The advantage to having a package is an additional capability
I would like to have for my designs is to be able to switch
polarity on clock and reset and between asynchronous and
synchronous reset for the entire design or limited set of IP
blocks in a trivial fashion - such as a package reference or
a binding to a package body (assuming that we give package
bodies names and ways to select them).

> 2. Shorthand for pipelining. This is another common operation that
> could be easier -- but it has significant side-benefits as well.
> Typically, pipelining a signal or an operation requires defining
> additional signals and/or variables to hold intermediate values,
> shifting values in and out, etc. Instead, VHDL could support something
> like the following inside a clocked process (perhaps limited to the
> syntax above).
> Product<= A * B after 2 cycles;

This could be a subprogram too:
    PipeReg(Clk, A*B, Result, 2) ; -- where 2 is the number of stages.

Implementation takes something that is not synthesizable right now:
    procedure PipeReg (
      signal Clk : std_logic ;
             ValIn : anonymous ; -- anonymous is another thing I would like
      signal Valout : out ValIn'subtype ;
             Stages : integer := 2
    ) is
      type PipeRegType is array (1 to Stages) of ValIn'subtype ;
      variable PipeReg : PipeRegType ;
        wait until Clk = '1' ;
        PipeReg := PipeReg(2 to Stages) & ValIn ;
        ValOut <= PipeReg(1) ;
      end loop ;
    end procedure PipeReg ;

However, if we put things like this in a standard library, they
don't have to synthesize it - vendors just have to know what it is.
For example, the function ieee.std_logic_1164.rising_edge
contains 'last_value which is not commonly synthesizable.

With an extra signal, I could rewrite the above procedure to
be compliant with current synthesis tools, or alternately
take advantage of VHDL-2008 aggregate changes and write it as
(it took me some reflection to realize I could even do this):

(Product, PipeReg(1 to STAGES-1)) <= PipeReg(1 to STAGES-1)&(A*B) when rising_edge(Clk) ;

If PipeReg were properly sized, then the above simplifies to:

(Product, PipeReg) <= (PipeReg & (A*B)) when rising_edge(Clk) ;

> 3. Object-oriented language features.
> 4. Verification language features.
These two are probably where I would like to focus my
involvement. My view is that OO is the base layer for
building verification language features.


Jim Lewis
Director of Training   
SynthWorks Design Inc. 
Expert VHDL Training for Hardware Design and Verification
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Received on Fri Feb 18 10:14:19 2011

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