[vhdl-200x] VHDL enhancements wish list

Here is my current wish list for VHDL language enhancements.

1. Shorthand for clocked process. It seems silly for an HDL to require
coding conventions to describe 90+% of designs, namely clocked
processes. Instead, (or in addition for the foreseeable future) VHDL
could support something like the following.

label: process clock(Clk) is
  -- declaration region for constants, variables, aliases, etc.
synchronous reset(Rst)
  -- reset logic
begin
  -- non-reset logic
end process;

For falling edge clocks, we could add another token to specify "process
falling clock(Clk) is ...." To be consistent we could also allow
"process rising clock(Clk) is ..." with the default a rising-edge clock.
For resets, we could allow either "synchronous reset" or "asynchronous
reset".

This change doesn't give a huge benefit, but it ought to be easy to
specify and use.

2. Shorthand for pipelining. This is another common operation that
could be easier -- but it has significant side-benefits as well.
Typically, pipelining a signal or an operation requires defining
additional signals and/or variables to hold intermediate values,
shifting values in and out, etc. Instead, VHDL could support something
like the following inside a clocked process (perhaps limited to the
syntax above).

  Product <= A * B after 2 cycles;

We could specify "clocks" instead of "cycles" if preferred, or possibly
allow either.

Besides the convenience, this approach has significant benefits in two
areas. First, this syntax makes it much easier for synthesis tools to
recognize and implement pipelined operations -- which is a big deal for
our FPGA designs. Second, this syntax allows formal verification tools
to see only the essential functionality. In other words, not only are
the extra objects and assignments annoying, but they *over-specify* the
circuit behavior. If the synthesis tool pipelines the operation like I
want, the formal tools will complain *correctly* that the synthesis
results do not match my design. This is because there is no way
currently to directly express pipelining.

3. Object-oriented language features. For a discussion of syntax and
benefits see e.g.

http://www.ashenden.com.au/suave.html

4. Verification language features. This is not a strong area for me;
in particular, I don't know SystemVerilog. But it seems that VHDL is
already relatively strong in verification features. The VHDL-2008 text
handling enhancements are a great improvement in this area. VHDL
already supports most of the ideas I hear described for SystemVerilog
verification systems. Adding object-oriented features should ease reuse
of verification IP. We ought to be able to propose several high-value
verification features that push VHDL back to parity -- or even beyond --
the functionality and ease-of-use of SystemVerilog. In particular, I
like the idea of stealing the best paradigms and features of
verification languages like e and Vera.

The other enhancements proposed have also sounded good to me. I look
forward to working with them in the process.

Enjoy!

---
Ryan Hinton
L-3 Communications / Communication Systems West
ryan.w.hinton@L-3com.com
 
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