[vhdl-200x] All please read: Out of Bounds Discussions

Hi,
Victor and I have talked off-line about the issue he
brought up and a couple of others that I was concerned
about.

---------------------------------------------
With regards to mentioning names:
1) If you need to discuss a product, please do not give
company names or product names, instead generically refer
to them. For example: simulator, synthesis tool, or FPGA tool.
Please do not use any abbreviation that divulges the name.
Such as vendor D when D is the first letter of the
company name.

[Note that it was me and not Scott that overlooked this
so any blame to the cause of this issue lies on me.
Scott only posted what I asked him to post after sending
it to me privatel. So if you were offended by the
email - I am sorry it happened.]

This comes from a long standing DASC tradition.
Victor is going to look into getting this formalized
in some document of the DASC or a higher level
IEEE group (if it is not already there).

---------------------------------------------
Other things that have come up:
In researching Victor's concern, I re-read the antitrust
document a couple of times and realized that some statements
that have been made in meetings or on the reflector are
not permitted due to anti-trust concerns:
http://standards.ieee.org/develop/policies/antitrust.pdf

2) Statements like the following,
   "If you add OO and Randomization constructs to VHDL, then
    we will not support them."
   "If you add OO and Randomization constructs to VHDL, then
    we will withdraw from the working group."

are statements of output restriction with respect to the
standard and are strictly forbidden by the IEEE antitrust
policies. In fact, this is one of the kind of violations
that if agreed upon by competitors can lead to jail time.
As a result, these type of statements are prohibited.

3) The antitrust polices also discourage cost discussions in
general. Here is one of the ones I saw on the reflector:
   #1 because OO is already built into SystemVerilog,
    and reinventing the wheel is too time consuming for this group,
    and is _too expensive_ for tool vendors who already
    have SystemVerilog and SystemVerilog/VHDL tool solutions.

As a result, in general, words like "cost" or "too expensive"
should not be used.

Thanks for reading.

Best Regards,
Jim Lewis
P1076 study group chair

-- 
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Jim Lewis
Director of Training             mailto:Jim@SynthWorks.com
SynthWorks Design Inc.           http://www.SynthWorks.com
1-503-590-4787
Expert VHDL Training for Hardware Design and Verification
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