[vhdl-200x] Reminder: Call for Vote (Repeat)

Sorry Jim,

there is one other headline I would like to add to my future wish list (last of
the '++' part). I hit the return button a second too soon.
Please discard the previous mail/vote.

Item 1: Working group organization, select one:
  ____X___ Individual
  ________ Corporate
  ________ Abstain

Item 2: 1076 PAR:
 http://www.eda-twiki.org/vasg/p1076_2014_draft_par.pdf
  ____X___ Approve
  ________ Negative
  ________ Abstain

Comments (optional with negative vote):
Desired scope of enhancements to future versions of VHDL standard:
++ Native language support for transaction level modelling
++ Native language support for randomised verification, UVM etc.
++ Native language support for IP encryption (P1735?)
++ Re-evaluation of interface to other languages, particularily SystemC and SV
++ Interchange format for simulation output (waveform dumps, traces etc.)
++ Tighter involvement with VHDL-AMS for mixed-signal system modelling

+ Improvements to TextIo

-- 
Best regards,
Mit freundlichen Gruessen,
Charles Gardiner
-------------------------------------------------------------
Ing. Buero Gardiner
Heuglinstr. 29a
D-81249 Muenchen
Email: mailto:gardiner.charles@vdi.de
Phone: +49 89/1400 6955, Mobile +49 171/867 2732
Fax  : +49 89/8638 9764
asic, eda, embedded hw/sw, fpga
soc, system verification
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