Re: [vhdl-200x] Strong Timing

> I agree with Jonathan that a lot of our time is spent on trying to meet timing. Probably working on this is a good move in the right direction too, as much of the verification of designs can already be handled by the core VHDL language. However, the language does not have enough constructs on imposing timing constraints.

Yes - moving constraints to the language seems like a very intelligent idea. Can anyone think of any drawbacks? I'm only able to think of positives at the moment.

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