[vhdl-200x] Re: VHDL Study Group Meeting Reminder and Details

From: Jim Lewis <Jim@synthworks.com>
Date: Tue Nov 30 2010 - 11:24:30 PST

I have had a couple of questions regarding should
I or can I attend the meeting.

The short answer is yes.

The long answer is, this meeting is open to all
with a vested interest in VHDL. If you are actively
using VHDL or developing tools for VHDL, you have
a vote in the meeting.

Also, before the meeting, please read the IEEE
patent policy:


> Hi,
> Study group meeting reminder:
> Wednesday Dec 1 at 8 am Pacific.
> Dial in 1-800-637-5822
> Intl Access: +1 647-723-3937
> Passcode: 6850837
> The main agenda will be to discuss and draft a PAR for
> P1076. Based on the previous PAR, I put together a draft
> for the next revision. I intentionally left the
> descriptions of work to be done generic to allow us
> freedom to do what the working group decides to do.
> I posted it here for your review:
> http://www.eda-twiki.org/vasg/p1076_2014_draft_par.pdf
> One discussion item will be the organization individual
> (as it has been) or corporate based working group.
> Here is a web page that describes the two options:
> http://standards.ieee.org/membership/index.html
> Also IEEE governing the rules of working group participation
> are here. In particular section gives the rules for
> entity based groups. These changes happened in
> http://standards.ieee.org/develop/policies/bylaws/sect5.html
> Either way we go, long term one thing we need to solve
> is how to fund any necessary items, such as funding LRM
> writing. Entity groups facilitate this - keep in mind
> though that all the IEEE dues go to IEEE - so no matter
> what we do we have to raise a separate amount of money
> to fund these activities.
> Another thing we need to solve is how to demonstrate
> that user companies are behind any proposed changes.
> We do not necessarily need to solve either of these
> last two items this while writing the PAR.
> Please attend and weigh in with your opinions on the
> PAR, group organization, and the additional issues.
> Best Regards,
> Jim Lewis

Jim Lewis
Director of Training             mailto:Jim@SynthWorks.com
SynthWorks Design Inc.           http://www.SynthWorks.com
Expert VHDL Training for Hardware Design and Verification
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Received on Tue Nov 30 11:24:58 2010

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