RE: [vhdl-200x] [Fwd: VHDL vector/matrix package?]

I disagree that it impacts synthesis.

For RTL synthesis, the semantics are clear: Each in the matrix will be synthesized
as normal signals (just like a normal array of arrays (of arrays...aso)), and if a
matrix operation is encountered, it must be completed in a single clock cycle.

It's not different from using, say a division operation. It could also be performed
using simpler operations over several cycles, but if used in RTL code, it must be
fully executed in a single cycle, according to RTL semantics.

Higher level synthesis algorithms aren't impacted much either (at least not
for compatibility reasons). Each matrix operation can be expanded into its
partial operations, and those partial operations can be scheduled as normal
scalar operations. How to represent and store object values, intermediate values
and schedule the operations is up to the tool.
If anything, tools will be aided by a higher level description because they
can use the higher-level operations to make some simplifications/synthesis/scheduling
decisions earlier before expanding them into scalar operations and making a
detailed schedule.

Or is there any facet of this that I'm missing?

I believe that your example use case is valid.
But it is in my opinion more related to "high level synthesis tools"
than to a language with built-in support for matrix/vector operations.

Regards,
Jonas Nilsson
Technical Staff
Synplicity Business Group
Synopsys, Inc.
Kalkstensvägen 3
SE-224 78 LUND
SWEDEN

Phone : +46-46-16 29 04
Fax : +46-46-16 29 01
E-mail: jonas@synopsys.com
web : www.synopsys.com / www.synplicity.com

> -----Original Message-----
> From: owner-vhdl-200x@eda.org [mailto:owner-vhdl-200x@eda.org] On Behalf
> Of Ernst Christen
> Sent: Tuesday, April 20, 2010 6:41 PM
> To: David Bishop; vhdl-200x@eda.org
> Subject: Re: [vhdl-200x] [Fwd: VHDL vector/matrix package?]
>
> Yes, I can see that for VHDL synthesis compatibility will be an issue.
> This is something we haven't seen with 1076.1 yet as there is no AMS
> synthesis. I think this raises two questions:
>
> Would a vector/matrix capability be useful without considerations for
> synthesis compatibility, for example for behavioral models used during
> verification?
> What additional requirements would be imposed to make vector/matrix
> operations synthesis compatible? Specifically, what scope are we talking
> about. For example, is something like synthesizing a signal processor
> given an algorithm a valid use case?
>
> Ernst
> --
> Ernst Christen, christen.1858@verizon.net on 4/20/2010
>
> > On 4/15/2010 9:26 AM, Jim Lewis wrote:
> >
> > > Has anything like this been considered for 1076, or do you know of
> an
> > > implementation of a proprietary package for this purpose? We have
> not
> > > gone far with it yet, we are still discussing requirements and
> scope.
> > > Any information you have will be helpful for out planning. I am also
> > > planning to consult with vhdl-200x to get feedback before we move
> > > beyond
> > > requirements.
> >
> > I started looking into this about 2 years ago. Lately I've been doing
> a
> > good deal of work with Matlab, and seeing how easy it is to manipulate
> a
> > matrix in that language. I'd like to see that sort of ability in
> VHDL.
> >
> > The big issue as I see it is synthesis compatibility. You pretty much
> > can't do this without the ability to infer a memory element. You also
> > need some sort of trade off between different types of memories.
> > How would you declare a matrix of X dimensions generically?
>
> --
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