Re: [Fwd: Re: [vhdl-200x] [Fwd: Re: Time to start up?]]

Matthias,

Re your request for delta cycle visibility. Modeltech does have this
feature in recent releases, and the user can toggle it on and off. I'm
not sure when it was put in place but I believe it has been there for
almost a year, so check any release from this time frame. There's
several buttons on one of the toolbars to control it.

I've only tried it once, but it did what I needed (teaching someone
about VHDL delta cycles). As with most new features in Modeltech it
seemed a bit temperamental, i.e. it didn't always seem to work as expected.

Regards,
James Goeke

Jim Lewis wrote:
> Forwarding something to the list that bounced
>
> -------- Original Message --------
> Subject: Re: [vhdl-200x] [Fwd: Re: Time to start up?]
> Date: Wed, 10 Mar 2010 21:23:52 +0100
> From: Matthias Wächter <matthias.waechter@tttech.com>
> To: Peter Ashenden <peter@ashenden.com.au>
> CC: Jim Lewis <Jim@synthworks.com>, vhdl-200x@eda.org
> References: <4B9510D3.1000208@SynthWorks.com>
> <4B978499.1000307@ashenden.com.au>
>
> Peter,
>
> Thanks for your reply. Indeed, the additions, or at least what I see in
> the unofficial changelogs, are really promising. Canâ??t wait to see
> someone start an OO thread to jump on :)
>
> Re 1: Umm â?¦ havenâ??t thought about precedence. Actually I donâ??t
> mind as I
> rarely rely on precedence. I built my own fab for parentheses, they
> never run out. :)
>
> Re 2: Wow, you actually *did* implement that ('subtype)! Great to see!
>
> Re 4/7: Really good. Next task is to look for synthesis vendors that
> claim full support for VHDL 2008.
>
> Re 6: I am sorry for the cryptic wording, and itâ??s just an idea of a
> sleepless night (in 2003), probably nothing for the standards committee
> to work on.
>
> Consider two unsynthesizable components, e.g. as part of a test bench. A
> use case would be a pattern generator driven by the test bench file
> parser module over a bus-like programming interface with address, data,
> ready and so on. To avoid the loss of real time and clock cycles which
> could affect simulation, the two blocks exchange information using delta
> cycles (for a limited number of cycles per time). This data exchange is
> typically not visible in wave windows of, e.g. ModelSim, as display of
> changes is solely time-driven (except if one steps through the processes
> as they are executed). Note that the textual listing of signals and
> related time does make delta cycles transparent, but uses a rather
> different UI, to say the least.
>
> Possible solutions for vendors:
> a) Allow all delta cycles to be enabled for display (e.g. toggle
> button). Will make most of the time scale discontinuous. â??Timeâ??
> spent in
> delta cycles could be emphasized by a different background color of the
> wave window.
> b) Allow the user to selectively unzip/zip delta cycles at specific
> times so the discontinuity is limited to that times and their delta
> cycles.
> c) Somewhat crazy: Allow the user to set up a non-zero delta delay (e.g.
> 1 fs). Will most probably break simulations because of slightly changed
> timing.
> d) ignore the feature request.
>
> Possible solution for me:
> e) Imply (d) and continue coding :)
>
>
> â?? Matthias
>

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