RE: [vhdl-200x] [Fwd: [Accellera:vhdl] Time to start up?]

How about a large integer/big decimal package?

I have been bitten a few times on overflowing the range of an integer in VHDL in some functions in DSP libraries I have built that can overflow 32-bit integer conversions pending on settings. As an example, I have a generic numerically controlled oscillator (NCO) with frequency sweep control that, pending on user constraints, can trip a VHDL error due to exceeding the size of the integer type. I have a work around to get by this but a large integer would be very useful in this case. It would also be useful to be able to create an unsigned 32-bit integer subtype which is currently prohibited due to the requirements on the current VHDL integer types and subtypes. This and larger integer sizes would be useful in CPU modeling. This would allow VHDL to have integer data types that can be identical to the size of the C/C++ integer types. I would expect the user would be required to define the range of such an integer and that synthesis tools should be able to synthesize it due to requiring a range definition.

If VHDL currently has the ability to do this, I would like to know. From the VHDL documentation I have read, the integer types are limited to 32-bits for signed, 31-bits for unsigned.

Regards,

Scott D. Hoy
E-mail: scott.hoy@itt.com
Phone: 301-497-9900 Ext. 7162
Fax: 301-497-0207

ITT-AES
141 National Business Pkwy. Suite 200
Annapolis Junction, MD 20701
Phone: 301-497-9900 Fax: 301-497-0207

-----Original Message-----
From: owner-vhdl-200x@eda.org [mailto:owner-vhdl-200x@eda.org] On Behalf Of Jim Lewis
Sent: Tuesday, February 23, 2010 10:13 AM
To: vhdl-200x@eda.org
Subject: [vhdl-200x] [Fwd: [Accellera:vhdl] Time to start up?]

-------- Original Message --------
Subject: [Accellera:vhdl] Time to start up?
Date: Mon, 22 Feb 2010 09:18:24 -0600
From: Lance Thompson <lancet@us.ibm.com>
To: vhdl <vhdl@lists.accellera.org>

Hi everyone,

In the immortal words of Roger Waters of Pink Floyd fame, "Is there
anybody out there?"

It's been a while since we released revision of VHDL to the IEEE and
took it through the ballot process to come out with 1076-2009. If my
memory is correct, we released it the IEEE early in 2008 and the IEEE
finished the ballot process at the end of 2008 or very early in 2009.
  At that point, I imagine everyone took a well deserved break from the
VHDL standardization activity. I know I did :-)

Since it's been around 2 years since we worked on details of the
language, I started to wonder if we should warm up the group and start
to drive any new changes to the language.

Any ideas?

Lance Thompson
IBM Technology Development
e-mail: lancet@us.ibm.com
office: 507.253.0145
mobile: 507.261.3607

--
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Jim Lewis
Director of Training             mailto:Jim@SynthWorks.com
SynthWorks Design Inc.           http://www.SynthWorks.com
1-503-590-4787
Expert VHDL Training for Hardware Design and Verification
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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