[vhdl-200x] 1076.6-2004 administratively withdrawn

Hi,
This is a FYI, 1076.6-2004 has been administratively withdrawn
by IEEE.  The following is an email explaining this.
In summary, no one at DASC level stepped forward and
supported it, so it was withdrawn.

Best,
Jim

-------- Original Message --------
Subject: Re: January Standards Administratively Withdrawn
Date: Wed, 13 Jan 2010 11:48:28 -0500
From: Victor Berman <vhberman@ieee.org>
To: Jim Lewis <Jim@synthworks.com>,	Stan Krolikoski <stanleyk@cadence.com>
CC: Karen Bartleson <Karen.Bartleson@synopsys.com>,	Werner Kathy-R65610 <kathy.werner@freescale.com>

Jim,

This was not done by accident.  Since this occurred during my term as Chair
I am taking the liberty to address this issue.  There was quite a bit of
discussion in the DASC about whether or not these standards should be
continued or withdrawn.  No one came forward to champion forming a new WG or
doing any work on them nor did anyone claim that they would be adversely
affected by the withdrawal.  The DASC voted to have them withdrawn and I
therefore made that request to the IEEE-SA and they are now withdrawn.

If someone thinks that there is a need for these standards or for an updated
version of them, they are free to request that an SG should be started and
to work toward drafting a PAR.

    Thanks,
     Victor

-------- Original Message --------
Subject: January Standards Administratively Withdrawn
Date: Wed, 13 Jan 2010 07:53:36 -0800
From: Jim Lewis <Jim@synthworks.com>
To: Stan Krolikoski <stanleyk@cadence.com>
CC: stds-dasc@server.eda.org
References: <201001121646.o0CGksfS007156@server.eda.org>

Hi Stan and all,
I just noticed the following were administratively withdrawn
in January.  Do we want to take some action to get them
reinstated:

1076.6-2004 IEEE Standard for VHDL Register Transfer Level (RTL) Synthesis

1364.1-2002 IEEE Standard for Verilog Register Transfer Level Synthesis


Best,
Jim
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Jim Lewis
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SynthWorks Design Inc.           http://www.SynthWorks.com
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Expert VHDL Training for Hardware Design and Verification
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