Dear colleagues, This is a call for vote from IEEE P1076 WG members on the next group of ISAC issues listed below. The ISAC has analyzed the issues and made recommendations for interpretation of the IEEE 1076-2002 standard and for future revisions of the standard. This vote is for approval of the ISAC recommendations. Please note that, in some cases, a recommendation may be to reject a request. In that case, a vote to approve the recommendation means rejecting the request, whereas a negative vote means reconsidering the request. Please take care with the logical sense of your vote in such cases. Also note that some of the issues do not specify detailed LRM edits to implement a change. The intention is that the detailed changes be specified in a Language Change Specification (LCS) document that will be voted on separately. The intent of this vote is to determine whether such an LCS is required. Only votes of eligible voters will be counted. Votes from ineligible voters will be recorded for information and for adding to your "last 2 or 3" participation count. I will acknowledge each vote received and indicate whether it was counted or not. Please forward votes to me by email (eg, by replying to this message) by 5pm US-PDT, Wednesday October 17, 2007. For each issue, would you please vote one of: approve, negative with comments, negative with no comments, or abstain. You may also provide informative comments with a vote to approve a recommendation. Please use the form below. Thank you. Regards, Peter Ashenden P1076 Secretary Issue Approve Negative Negative Abstain with comment no comment 1000 Accumulated typographical and terminology errors. http://www.eda-twiki.org/isac/IRs-VHDL-2002/IR1000.txt 1000 ____ ____ ____ ____ Comment: 2111 Unknown term used: selector http://www.eda-twiki.org/isac/IRs-VHDL-2002/IR2111.txt 2111 ____ ____ ____ ____ Comment: 2115 Binding specification should be binding indication http://www.eda-twiki.org/isac/IRs-VHDL-2002/IR2115.txt 2115 ____ ____ ____ ____ Comment: 2116 What is the direction of std_logic_vector & '0' http://www.eda-twiki.org/isac/IRs-VHDL-2002/IR2116.txt 2116 ____ ____ ____ ____ Comment: -- Dr. Peter J. Ashenden peter@ashenden.com.au Ashenden Designs Pty. Ltd. www.ashenden.com.au PO Box 640 VoIP: sip://0871270078@sip.internode.on.net Stirling, SA 5152 Phone: +61 8 7127 0078 Australia Mobile: +61 414 70 9106 -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean.Received on Tue Oct 2 20:37:12 2007
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