Dear Colleagues, Currently the Accellera Enhancements group is working on enhancements to VHDL in the area of Interfaces, Constrained Random, Functional Coverage, and OO. We specifically would like to recruit more users to get involved in this effort so we end up the features and methodology that solves your issues. I realize that the current meeting time for the enhancement group may be inconvenient for some. The time is negotiable based on participation. If you are interested in participating and the current meeting time does not work for you, please respond to this and let us know meeting times that would work for you. Please also CC Ajay Varikat, the enhancements chair (ajay@cadence.com), and myself (jim@synthworks.com). I am also thinking that perhaps an in person meeting sometime in October or Novemeber may be a good idea. Let us know if you are interested and when. Best Regards, Jim -- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Jim Lewis Director of Training mailto:Jim@SynthWorks.com SynthWorks Design Inc. http://www.SynthWorks.com 1-503-590-4787 Expert VHDL Training for Hardware Design and Verification ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~Received on Fri Sep 22 09:17:08 2006
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