Re: [vhdl-200x] Review of FT-32

From: <tgingold_at_.....>
Date: Wed Aug 10 2005 - 07:28:25 PDT
Selon John Ries <>:

Just a remark, as an author of a vhdl simulator:

> P1: PROCESS ( Design.E(A).C2.E2.p1 )  -- is this an error?
>                                                                       -- we
> can't tell until the design is elaborated.
>      ASSERT ( Design.E(A).C2.E2.p1 = '0');
> END;
I don't think this is possible.  If it is not possible to detect wether
Design.E(A).C2.E2.p1 is an error, then you don't know its type too.  Then
you can't analyze any expression containing such an expanded name.

In this example, which "=" the "=" refers to ?

I think it is possible to allow hierarchical names with at least a restriction:
* all the prefixes must have been analyzed.
This restriction must be verifiable at analysis time.

For example, inst1.ent(arch).blk.sig
INST1 is a component instantiation label.  But it instantiates either a
configuration, or an entity with an architecture.  Furthermore, the
configuration (if any), the entity and the architecture have been analyzed.

Received on Wed Aug 10 07:32:06 2005

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