RE: Re: [vhdl-200x] Review of FT-32

John:

You wrote:

To the extent that you appreciate the nature of requirements in this 
area and are willing to offer your point of view on them, I hope you 
will contribute to the ongoing requirements discussion in Accellera.  To 
the extent that you are motivated to identify issues and potential 
conflicts with the proposals, I hope you will also continue.  I only ask 
that you bear in mind the process we are trying to follow to get it 
right and where Accellera is in the process.

The thread "Review of FT-32" started as Erich pointed, with an answer 
a request, he writes:

Just to clarify - my email yesterday was the result of a request to review the 
FT-32 proposal that was made in June by John Shields. 

(note that it is not clear form Erich phrase if the request or the proposal was 
made in June by John, but in any case there was a request to start this review)

It continued with other comments and questions like 
the one form Steve:

(this was done while the new plans to start from requirements were known)

For us simple minded folks, can you provide an example with aliases that
creates additional problems? 

To which I answered with some simplistic analysis. 

Now you see that probably this thread got too far ahead, given the fact 
that requirements are still discussed, and tell me (only) what to "bear in mind"
as if I was the only one discussing the topic, fair? 

I do not know why you take the time to state that it is 
OK for me to _continue_ with two categories of contributions.
I know what I can do, what you already have as my 
contributions, and any rationale behind my actions. 
Do I need a special "green light" to _continue_? Please 
let me know.

In conclusion, do I have to jump on a "high horse" 
to gain the first class status in this effort?

Regards,

Alex Z

-- 
Alex Zamfirescu
azro@onebox.com - email
(877) 332-0676 - voicemail/fax




-----Original Message-----
From:     John Shields <John_Shields@mentor.com>
Sent:     Tue, 09 Aug 2005 13:19:22 -0700
To:       azro@onebox.com
Cc:       SBailey@model.com;vhdl-200x@eda.org;vhdl-200x-ft@eda.org;vhdl@lists.accellera.org
Subject:  Re: [vhdl-200x] Review of FT-32

Alex,

You posed a question and my answer is that I do think we should "go to 
school" on the Verilog implementation experience, but I think it 
critical that we capture good use models first. (bad ones, too).  We 
have to talk to the users trying to use them in Verilog or who desire to 
use similar features in VHDL.  This guides the language design and 
analysis, but it does not constrain us to satisfying every desire. 

I appreciate your cautions and the fact that there may be more as yet 
unforseen problems.  I think it is precisely because VHDL has such 
well-defined semantics that we can craft a use model and design for 
out-of-scope references effectively.  First, we have to define the 
requirements for the capability to capture user needs and desires.  It 
is clear to me that writing more effective testbenches and enabling ABV 
are a couple.  Then we have to design the language enhancements with a 
clear intent not to allow deadlocks, loops, and other 
non-determinisms.   Erich proposed a syntax to address a problem with a 
set of proposed enhancements; as I saw it, a framework for satisfying 
the needs.  We have not defined the semantics.  It has not been fully 
analyzed, but your feedback brought some of the analysis considerations 
forward early.  Accellera is now aimed at capturing a good set of 
prioritized requirements for which (I expect) this syntax with 
appropriate semantics will become one proposal.   There certainly is 
another variation using subprograms that addresses some of the expected 
requirements. If we have to reject or refine some user-driven 
requirements, we'll do it and get consensus on solving the right 
problems. I believe that a successful final proposal will be crafted.

To the extent that you appreciate the nature of requirements in this 
area and are willing to offer your point of view on them, I hope you 
will contribute to the ongoing requirements discussion in Accellera.  To 
the extent that you are motivated to identify issues and potential 
conflicts with the proposals, I hope you will also continue.  I only ask 
that you bear in mind the process we are trying to follow to get it 
right and where Accellera is in the process.

Regards, John
 

azro@onebox.com wrote:

>Steve:
>
>I thought more and realized that relaxing name restrictions
>would also make possible to initialize objects (constants for 
>example) to values of objects declared in a lower level block
>that are initialized to the higher level object values.
>
>Such objects would be documented as initialized but their 
>initial value would be "just a guess." 
>
>Attribute declarations could also get be in trouble.
>
>Fixes to the proposal would therefore require:
>1. Definition of the special selected name (call those "drifted 
>selected names" or DSNs) because not all selected names 
>should be excluded.
>2. New (probably complicated) rules about where those 
>DSNs could be used.
>Note that languages that let you use such DSNs (like Verilog)
>do not have the "declare before use" rule. However, even 
>so the propagation of the parameter values in Verilog is 
>still a mystery (read, under investigation by each implementer).
>So to find if those DSNs are good we should not ask those 
>who try to use them in Verilog, but those who try to implement 
>them. 
>
>Remember that an Ariane racquet exploded a few seconds after 
>launch due to just one wrong 32 to 64 conversion. Getting more 
>guessing into the standard would only increase the chances for a 
>repeat. I hope it will not be on your or my car airbag system. 
>
>Regards,
>
>Alex Z
>  
>