Subject: Re: [vhdl-200x] Approval for Merger of 1164 into 1076
From: Wolfgang Roethig (wroethig@necelam.com)
Date: Mon Feb 23 2004 - 14:33:28 PST
Hello all,
I approve this proposal.
Best regards
Wolfgang Roethig
> From: "Bailey, Stephen" <SBailey@model.com>
> To: "'vhdl-200x@eda.org'" <vhdl-200x@eda.org>
> Subject: [vhdl-200x] Approval for Merger of 1164 into 1076
> Date: Sun, 22 Feb 2004 16:12:36 -0800
> MIME-Version: 1.0
> X-Scan-Signature: 7407727619d5e6d1f8cf87459ab789e5
> X-Scanned-By: SKYnet 2.0
>
> This is a call for vote. The issue being voted on is:
>
> Approval of the merger of 1164 standard into the 1076 standard.
>
> ___ Approve (comments are optional)
>
> ___ Disapprove (please provide comments)
>
> ___ Abstain
>
>
> Background:
>
> The 1164 standard defines the package std_logic_1164 which defines the std_[u]logic
and std_[u]logic_vector types, resolution function and various overloaded and
non-overloaded operations on these types. The 1164 standard is defined entirely in
legal VHDL source code.
>
> The benefits of merging the two standards include:
>
> - Easier maintenance in keeping the two standards synchronized. (The importance of
synchronized maintenance is very high considering that something approaching 100% of
designs use this package.)
>
> - Ability for 1076 to more proactively analyze, research and resolve requests for
enhancements to 1164 in ways that may require language enhancements to maximize the
value. (For example, some ability to exploit std_logic's don't care ('-') state such
that it can be used in matching/equality expressions and in case statements.)
>
> - Reduction in DASC bureaucracy and, hopefully, an increase in operational
efficiency of the two tightly related groups. Although not a primary consideration, the
DASC SC, at the recent DATE meeting, did request that both 1164 and 1076 WGs explore the
merger of the two groups.
>
> While merging these two WGs would establish a precedent of sorts, it by no means
indicates that all 1076-related standards will be merged into 1076. For many
1076-related standards (1076.6, 1076.1, 1076.1.1 and, probably 1076.3), there are
reasons to keep the WGs separate. For example, 1076.6 defines synthesis
semantics/inference while 1076 defines simulation semantics; 1076.3 (math packages)
could be generalized to cover Verilog as well as VHDL and the 1076.1 and 1076.1.1 WGs'
scope is analog whereas 1076 is digital. Therefore, please evaluate this proposed
merger solely within the context of what is proposed.
>
> Peter Ashenden, as chair of 1164, is concurrently seeking the approval of the 1164 WG
membership for this merger.
>
> Please submit your vote to me (sbailey@model.com) by 8 March 2004. Any discussion can
be submitted to the entire WG at vhdl-200x@eda.org.
>
> Thank you.
>
> ------------
> Stephen Bailey
> TME, Mentor Graphic's Model Technology Group
> sbailey@model.com
> 303-775-1655 (mobile, preferred)
> 720-494-1202 (office)
> www.model.com
>
This archive was generated by hypermail 2b28 : Mon Feb 23 2004 - 14:53:57 PST