Subject: Re: [vhdl-200x] Corrections to Minutes for VHDL-200X-FT meeting, San Jose Dec 4, 2003
From: Evan Lavelle (anti.spam1@dsl.pipex.com)
Date: Fri Dec 19 2003 - 11:36:47 PST
Ok, if I've understood you correctly, I was going to cover exactly this
point in my last mail, but I decided it would make it too long and
nobody would bother reading it. As you say, "We cannot protect everyone
from making all mistakes". but consider this, to expand my last example:
The user had intended to write
if we = '0' ...
but instead got distracted and wrote either
1) if we ...
or
2) if we = '1' ...
(2) is a plain and simple logic error; brain fade. No tool can be
expected to protect against this; the designer just got it wrong. That's
what simulation is for.
(1) is completely different. If the language is strongly typed, then the
compiler *knows* that the user made an error. If we add an implicit
COND, however, then the compiler doesn't know, and the user may never
find out.
Our job is to ensure that the designer gets as much help as possible
from the compiler. Surely we can't throw out type safety just because
compilers can't find logical errors? This would be throwing out the baby
with the bathwater.
Evan
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