Subject: Re: [vhdl-200x] Corrections to Minutes for VHDL-200X-FT meeting, San Jose Dec 4, 2003
From: Munden Rick (Rick.Munden@Siemens.com)
Date: Sun Dec 14 2003 - 21:51:50 PST
My comments are embedded.
Bailey, Stephen wrote:
> I see no differentiation between ease of typing and reading. They are
> the same to me.
Try reading something someone else typed.
> In general, longer descriptions are harder to read as the same
> information scrolls off to the right (unreadable in many text editors
> without scrolling or cropped from a listing printout) or requires the
> reading of multiple lines instead of a single line (either due to manual
> or editor breaking of lines).
I suppose this could be true on a laptop computer (the scrolling part
that is). Generally, I find reading a paper easier (assuming I need to
understand it) than reading the corresponding powerpoint presentation.
> But, I will acknowledge that there is subjective opinion on whether one
> is harder than another. However, my experience (much wider than just
> VHDL) indicates that your opinion (preference over longer names vs.
> shorter) is in the minority. Since I want the VHDL user community to
> grow, I want our focus to be on the market majority.
Then I cast my vote with the minority. Wait a second, how do I know I
am in the minority until the votes are counted?
> As a marketing person, I cannot credibly argue the value of verbosity
> for verbosity sake and I certainly cannot tell people that they should
> choose VHDL over Verilog because we have to_string instead of to_str. I
> can persuade people to use VHDL over Verilog if, with the same effort
> (productivity) or less, you get a hardware description that has a
> significantly greater probability to be bug free. There are many
> studies that show that the bugs per line of code is relatively constant
> from assembly through C++ or Java (across any abstraction level).
> Concise descriptions are valuable as they reduce the lines of code and
> opportunity for bugs.
For many of us, it is not just about writing code, it is also about
> Hopefully, I have persuaded you or others. If not, we will need to
> agree to disagree on this issue and see how things work out. However, I
> do want you to know that I recognize your contributions on other issues
> and appreciate your participation.
Sometimes it is appropriate to build in stucco and other times in stone.
We don't need to merge VHDL and Verilog to come out with something in
the middle. Each language has its place. I would rather see us
concentrate on adding actual capability than just adding shortcuts.
> -Steve Bailey
>>Bailey, Stephen wrote:
>>>However, I must admit to not comprehending what is causing
>>all of this
>>>Is To_Str not understandable? Is "str" so infrequently
>>used that no one
>>>can be expected to realize it is an abbreviation for "string"?
>>It's understandable, but not as readily as to_string. String is a
>>complete English word, str is not.
>>>The benefit of typing fewer characters due to the use of
>>>abbreviations is just that, a benefit. There is no negative here.
>>It's quicker to type str, but IMHO it's quicker to read
>>string. So which
>>function is more important, reading or writing? I think reading wins,
>>especially given that you can have your editor expand the
>>>In other areas, we could argue as to whether or not "slv" is an
>>>appropriate abbreviation for "std_logic_vector". However,
>>I would note
>>It's nice to type (so I have my editor configured to expand it), but
>>it's no easier to read.
>>Hamish (not speaking for Agilent)
>>Data Networks Division
>>+61 3 9210 5782 (T210 5782) Tel
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