RE: [vhdl-200x] Corrections to Minutes for VHDL-200X-FT meeting, San Jose Dec...

Subject: RE: [vhdl-200x] Corrections to Minutes for VHDL-200X-FT meeting, San Jose Dec...
From: Bailey, Stephen (
Date: Sun Dec 14 2003 - 18:57:59 PST


Looks like I was a little bit convincing.

On a detailed proposal: Jim and his team will need to write one up.

On the lack of complaint from Verilog users: True. We don't want the requirements of the arbitrary hacker to drive VHDL's evolution. But, there are plenty of reasonable Verilog designers as well.

-Steve Bailey

> Hi Stephen,
> Giving it a second or third thought, implicit boolean equivalence
> might not be that evil.
> From a pure user's perspective (leaving aside detailed knowledge about
> language mechanisms for a moment), we do a lot of what very close to
> implicit type conversion already. We just call it overloading.
> given the declaration:
> unsigned u1, u2;
> what I enjoy is being able to type is:
> u2 <= u1 + 1; -- or '1' for std_logic
> , where the integer literal `1' is (from a user's perspective)
> implicitly converted to an unsigned value.
> So having an implicit conversion to boolean in certain well-defined
> places might not be such a bad idea. And, as you pointed out, nobody
> has to use it. I am not yet decided whether I will or not.
> As far as (unintentional) misuse is concerned, I cannot think of a
> particular example where that would be possible using the mechanism
> you suggested. Has anyone else thought about potential issues?
> In particular we won't be able to see things like the famous C-blunder
> if (a = b) { /* should that have been `==' ? */
> }
> What I think most VHDL users require is that the language remains easy
> to read (and write) and that a Lint tool does not become a mandatory
> investment (it is for The Other HDL). We want VHDL compilers to be
> able to point us to subtle errors every one of us makes in daily life,
> before we run a simulation.
> IMHO, the most important thing for everyone who was not at the meeting
> to judge (if only I could...), is a detailed version of the last slide
> in the presentation Jim posted. Where can I find one?
> Best regards,
> Marcus
> PS:
> Bailey, Stephen writes:
> > If this were a huge problem, Verilog users would be complaining
> > about it. They are not.
> I hardly consider this a convincing argument, but still.
> --
> Marcus Harnisch | Mint Technology, a division
> of LSI Logic
> | 200 West Street, Waltham, MA 02431
> Tel: +1-781-768-0772 |

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