Re: [vhdl-200x] Minutes for VHDL-200X-FT meeting, San Jose Dec 4, 2003

Subject: Re: [vhdl-200x] Minutes for VHDL-200X-FT meeting, San Jose Dec 4, 2003
From: Hamish Moffatt (hamish_moffatt@agilent.com)
Date: Wed Dec 10 2003 - 14:59:31 PST

Matthias Wächter wrote:
> Similarly to Jonas's input, it would be a great benefit to have access to
> not only the base type of a type (using type'base or sub_type'base) but
> also to the type of a variable/constant or signal. This would improve
> object-oriented approaches and code re-use. Underlying ranges of the base
> type can already be taken from signals, but not the base type itself.

Similarly, it's a nuisance that having declared

signal n: integer range 0 to 15;

you can't write n'high, but instead must use

subtype type_of_n is integer range 0 to 15;
signal n: type_of_n;

and use type_of_n'high.

> Additionally, what I'd like to see in VHDL and what should be no big deal
> is a way of using ranges in aggregate assignments - the only range that
> can be used is the term 'others'. For example (sorry for the excessive use
> of subtypes/ranges):

Hear hear.

Is this the right place (& time?) to be discussing this? Is one of the
other lists more appropriate?

regards,
Hamish 

-- 
Hamish Moffatt
R&D Engineer
Data Networks Division
Agilent Technologies
+61 3 9210 5782 (T210 5782) Tel

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